Other Parts Discussed in Thread: CC2340R5, SYSCONFIG
Tool/software:
Hello TI Tech Team,
we are planning to use CC2340R2 wireless SoC and *****>
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Hello TI Team,
While reviewing the Ref. Design schematic page 2 of CC2340R5, I have found possible mistakes.
1) R55,R56 are connected to GND through SW2 and SW1 on one side, and other side to DIO9_BTN2, DIO10_BTN1. Both DIO9 and 10 are NOT high current capable. As per the DS, they can handle only 2mA current. But the value of R55 and R56 shown is only 100Ohms. So, when a switch button is pushed, with Vdd 3V, the current flow will be (0.8x3V) = 2.4V/100 = 24mA. This is almost shorting pins DIO9 and 10 to GND resulting in burning the chip. Even if both DIO9, 10 were high current capable, they can handle 10mA max. as per the DS page 35.
2) BOM also show 100 ohm values for both R55, R56.
Don't you think the value should be 100K...?? Like R1.
Hello AB,
I appreciate your candid feedback and have notified the TRM developers about your grievances. They will also be able to support your reference design questions.
About entering low-power modes on the CC2340R devices, it is true that the Power TI Driver is the preferred method for managing this behavior. If there exist bugs in the driver then bug tickets are filed to review and fix such errors. However it is possible to subvert any TI Driver solution and use your own low-power firmware.
Hope this helps,
Ryan
Hi
1. Regarding the mechanical drawing, what are you looking for in pages 71 -78 that is missing? As for the YBG, this package has not been official released yet, but we can provide the footprints and package info.
2. In our reference design, DIO9_BTN2 and DIO10_BTN1 are used and configured as inputs where drive strength is not relevant. The capacitive input of each DIO pins would prevent any sort of high current. The 100 ohm is used as placeholder for the customer to configure it as they see fit. If these DIOs were configured as an output driving a load, then drive strength would be a concern.
Best regards,
Bun
Hello Tech Team,
There are serious glitches in ur software package of this forum. The text of my original question is all missing except one line above ending with *****>. Therefore I am rewriting the same below. (I am glad I had saved that text in my computer.)
we are planning to use CC2340R2 wireless SoC and MSPM0G35 MCU in our new product line (10-12 devices). While MSPM0G35 documentation in the DS and the Tech Reference Manual is well written, some essential info in the CC2340R2 DS and Tech Reference Manual is inadequate/missing. I have spent more than 3-4 days searching through DS and Tech Ref Manual (1300+ pages), and still did not find.
I am looking for the specific info - how to enter each Operating Mode (Power Mode) and how to exit.
Searching on the Internet and TI Tech Forum, the only answers I found was how to do it in the software - TI's drivers etc. We are NOT looking for such info which is obvious. (What if there are bugs in the driver...?) Software has to implement this function at the hardware level - configuring some control registers (at the bit level) of the chip, and executing some specific instructions similar to MSPM0G35.
1) Operating Modes of MSPM0G35 - Section 8.2 of MSPM0G35 data sheet (DS) gives basic info about exiting (Wakeup) the Operating Modes, including in Table 8-1.
Section 2.1 of the Tech Ref Manual gives detailed info about all modes, including exiting (Wakeup) info in Table 2-1. Section 2.4.2
Operating Mode Selection gives register level information about how to configure each mode. And above all, it gives info about how to Enter each mode. We have no issues here.
2) Power Modes of CC2340R2 - In both the DS and the Tech Ref Manual, Operating modes are referred as Power Mode for this SoC. Section 8.11 Power Management of the DS gives basic info about exiting (Wakeup) the Power Modes, including in Table 8-3. There is no detail anywhere in the DS about how to exit.
Note: Is there a typo in the following line under the table 8-3:
(2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode
Should the word be content and not context...? Please correct.
2.1) 6.2 System CPU Modes of the Tech Ref Manual states:
"The CPU modes, Run, Sleep, and Deep Sleep, are managed by the TI Power API and cannot be directly manipulated."
Section 6.4.2 Shutdown says: "The lowest power state that can be deliberately entered by software." No info is given how to enter shutdown state. Basic info about Wake-up is given, but no details how.
Further section 6.4.5 Standby describes functioning and exit (wake-up) from this mode, but no details how. No info is given how to enter Standby mode.
Section 4.3.4.3 Power Management Controller (PMCTL) describes the Wake-up event from the Standby mode in more details, but not completely. Table 4-4 has more details on Wake-up events, but incomplete, and also there are many mistakes in the table, for example:
GPIO combined wake up interrupt, interrupt flags can be found here GPIO.MIS
I searched entire manual, but GPIO.MIS is not written anywhere else.
There are similar mistakes in Table 4-18, for example:
9h = GPIO combined wake up interrupt, interrupt flags can be found here GPIO:MIS
Fh = SPI0 combined interrupt request, interrupt flags can be found here SPI0:MIS
Note: After lot of search, coincidentally, I found some useful info in:
Table 4-12. WKUPMASK Register Field Descriptions
This table defines six AON_..... interrupt masks register bits, e.g.:
Wake-up mask for AON_IOC_COMB.
0 - Wakeup Disabled
1 - Wakeup Enabled
... just too many mistakes/issues to list.
Section 6.11 PMCTL Registers - Table 6-71 lists/describes all registers of the Power Module Controller. The Go link goes to the specific register where bit-level details are given about how to enter a specific mode, or Enable/Disable a mode.
6.11.3 SHTDWN Register defines the key value A5A5h to enter Shutdown Mode. Great!
6.11.4 SLPCTL Register defines how to Enable/Disable Sleep Mode.
Still no info about how to enter Standby Mode.
3) Mechanical Packaging - The Info about the chips (40 pin, 24 pin and YBG) in the DS of CC2340R2 is missing - an important one. Is it in some other document? We need this to do PCB layout design - this is a SHOW stopper, please provide this info ASAP.
Note: This Packaging info is always shown in the DS of every chip. Example: MSPM0G350x. Please update this in the next version of the DS of CC2340Rx.
RECOMMENDATION
Please write a section "Power Modes" in the DS of CC2340R2 similar to Operating Modes section in MSPM0G350x, where customers can find info at one place. And send that section and also the Mechanical Packaging info to me by email so that we can continue.
CONCLUSION
I am exhausted doing above task of finding problems with the CC2340R2 DS and Tech Ref Manual, which should have been written correctly before publishing for customers. Please escalate this issue to higher management, and assign some tech person(s) to go through both docs, and correct everything - even items I did not find time to search in 1300+ pages. At present, we have to halt our design work using this MCU. And I wonder if TI has sold any of these chips...!!!
Thanks.
Hello Bun,
NOTE: I could not see the entire text of my original Posting above - only one line is visible ending with *****>, so I have rewritten the same in my reply. It is apparent,somehow, that you are able to read my whole text. So, let me come to my Q about mechanical packaging of CC2340R2 chip.
1) You have mentioned pages 71-77. But the datasheet of CC2340R has only 65 pages. Which DS are you looking at?
Please read my question again. We (and all other customers) absolutely need the Mechanical drawings Info similar to MSPM0G350x DS pages 80-95. There is nothing in the DS of CC2340R2. Without it, we cannot do the layout of the chip.
Thanks.
Hello Bun,
2) Regarding my Q about DIO9_BTN2 and DIO10_BTN1, you have written about the Capacitive inputs. I need further details please. Does it mean that when DIO9 is configured as Input (non-open drain), there is some pull-up resistor (100K etc) inside the CC2340R chip and the Button BTN2 input goes to the Gate of a MOSFET? In that case, sure current will be limited by the resistor inside the chip.
And in such case, do I really need R55, R66 etc.? The current should be limited in both conditions - BTN2 open and closed. If I don't need R55, R56 etc., I can save some space on my PCB (by not installing such resistors. Our PCBs are very small.
Thanks.
I just found some info on page 35 of the CC2340R datasheet. It mentioned both Pull-up and Pull-down resistors, and also Vpad. The Vpad is not defined anywhere in DS, but I assume it is the input at DIO9 pin. In that case, when Button is OPEN, the input is floating, and when it is closed, it is 0V (GND). So, how should the DIO9 be configured? Would configuring it as Input is enough? Don't need to worry about pull-up or pull-down resistors?
Sorry I am asking these basic questions - because I don't know what circuit is at the DIO pins.
Thanks.
Hello Bun,
Sorry about the confusion about the DS. I had downloaded the CC2340R DS from Digi-Key site few months ago, which has only 65 pages. Surprisingly, the revision date on both DS is Sept. 2024. TI updated the DS and added pages after 65, but did not update the Revision date. And that is why I did not download from TI website.
Hi,
1. This is the link to the datasheet I'm referring to: https://www.ti.com/lit/gpn/cc2340r2
2. Correct, all DIOs goes to the gate of MOSFET and configured to be pulled up by 100k ohm by default
3. You do not need R55 and R56.
4. Vpad refers to the voltage level applied at that pin/pad.
5. When a button is open it is pulled up internally with a 100k ohm resistor, but this must be configured in sysconfig. No DIO pins should be floating.
When it is closed/grounded there's nothing to be done. Input or output, the voltage is simply 0V at the pad/pin.
Best regards,
Bun