CC2745R10-Q1: RTC adjust

Angela Zou

Part Number: CC2745R10-Q1
Other Parts Discussed in Thread: CC2340R5

Tool/software:

Dear expert,

I suggest customer follow the instructions below: software-dl.ti.com/.../debugging-index-cc23xx.html. But they can not output 32k waveform through GPIO.

Here is the codes:

static void lf_debug(void)

{

uint8_t clockSrc = 0xE; //C; //for HF crystal clock divided by 8

// uint8_t clockSrc = 0xF; //for LF crystal clock

// drive output low first

GPIO_setConfig(19, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);

// Configure the IOC.IOC19.PORTCFG MMR to select DTB

HWREG(IOC_BASE + IOC_O_IOC19) &= ~IOC_IOC19_PORTCFG_M;

HWREG(IOC_BASE + IOC_O_IOC19) |= IOC_IOC19_PORTCFG_DTB;

// Make sure the DTB mux selects in IOC (and if required in

// source clock IP) are reset that zero is driven on DTB0.

// ULLSEL mux select (select CKMD)

HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;

HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0

// Enable IOC.DTBOE.EN0

HWREG(IOC_BASE + IOC_O_DTBOE) &= 0x10; //~IOC_DTBOE_EN0_M;

HWREG(IOC_BASE + IOC_O_DTBOE) |= 0x10;//IOC_DTBOE_EN0_EN;

// select which clock (CKMD) to output on DTB0 (DTB[0])

HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;

HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;

// enable DTB output

HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;

HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;

}

According to the following code, when they reduce the high-speed crystal oscillator frequency by 8 times, it can output 6M at the DIO27 pin, but when switch to the internal clock, it cannot output it. How to match this?

static void lf_debug(void)

{

uint8_t clockSrc = 0xC; //for HF crystal clock divided by 8

// drive output low first

GPIO_setConfig(27, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);

// Configure the IOC.IOC19.PORTCFG MMR to select DTB

HWREG(IOC_BASE + IOC_O_IOC27) &= ~IOC_IOC27_PORTCFG_M;

HWREG(IOC_BASE + IOC_O_IOC27) |= IOC_IOC27_PORTCFG_DTB;

// Make sure the DTB mux selects in IOC (and if required in

// source clock IP) are reset that zero is driven on DTB0.

// ULLSEL mux select (select CKMD)

HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;

HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0

// Enable IOC.DTBOE.EN0

HWREG(IOC_BASE + IOC_O_DTBOE) &= ~IOC_DTBOE_EN0_M;

HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN0_EN;

// select which clock (CKMD) to output on DTB0 (DTB[0])

HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;

HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;

//HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~DTBCTL_DSEL0_M;

//HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= 0x4 << IOC_DTBCFG_ULLSEL_S;

// enable DTB output

HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;

HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN;

}

1 month ago

0 Nima 1 month ago

TI__Genius 14705 points

Hello,

I apologize for the delay. The pins in that code are for the CC2340R5, and have changed for the CC27xx.

Do you mind trying the code below:

 /*******************************************************************************
    * INCLUDES
    */
    #include <ti/drivers/GPIO.h>
    #include DeviceFamily_constructPath(inc/hw_types.h)
    #include DeviceFamily_constructPath(inc/hw_memmap.h)
    #include DeviceFamily_constructPath(inc/hw_ckmd.h)
    #include DeviceFamily_constructPath(inc/hw_ioc.h)
    #include DeviceFamily_constructPath(inc/hw_pmctl.h)
    
    // ...
    
    int main()
    {
        // ...
        
        /*
         * Add the following after Board_init();
         * Be sure IOID used below is not used by any entries in PIN or
         * GPIO tables from the board files.
         * The clock source can be switched with constant clockSrc.
         */

        //uint8_t clockSrc = 0xC; //for HF crystal clock divided by 8
        uint8_t clockSrc = 0xF; //for LF crystal clock// drive output low first

        // drive output low first
        GPIO_setConfig(27, GPIO_CFG_OUTPUT | GPIO_CFG_OUT_LOW);

        // Configure the IOC.IOC19.PORTCFG MMR to select DTB
        HWREG(IOC_BASE + IOC_O_IOC27) &= ~IOC_IOC27_PORTCFG_M;
        HWREG(IOC_BASE + IOC_O_IOC27) |= IOC_IOC27_PORTCFG_DTB;

        // Make sure the DTB mux selects in IOC (and if required in
        // source clock IP) are reset that zero is driven on DTB0.
        // ULLSEL mux select (select CKMD)
        HWREG(IOC_BASE + IOC_O_DTBCFG) &= ~IOC_DTBCFG_ULLSEL_M;
        HWREG(IOC_BASE + IOC_O_DTBCFG) |= 0x1 << IOC_DTBCFG_ULLSEL_S; // 0x1 to route CKMD to DTB0// Enable IOC.DTBOE.EN0

        // Enable IOC.DTBOE.EN0
        HWREG(IOC_BASE + IOC_O_DTBOE) &= ~IOC_DTBOE_EN0_M;
        HWREG(IOC_BASE + IOC_O_DTBOE) |= IOC_DTBOE_EN0_ENABLE;// select which clock (CKMD) to output on DTB0 (DTB[0])

        // select which clock (CKMD) to output on DTB0 (DTB[0])
        HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_CLKSEL_M;
        HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= (clockSrc) << CKMD_DTBCTL_CLKSEL_S;// enable DTB output

        // enable DTB output
        HWREG(CKMD_BASE + CKMD_O_DTBCTL) &= ~CKMD_DTBCTL_EN_M;
        HWREG(CKMD_BASE + CKMD_O_DTBCTL) |= CKMD_DTBCTL_EN; 
        
        // ...
    }

Best,

Nima Behmanesh

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CC2745R10-Q1: RTC adjust