CC2340R5: GPIO interrupt delay to much when enable J-link RTT

Hi Zhang,

 CC2340R5: GPIO interrupt delay  

Please refer to PowerCC23X0.c where PowerCC23X0_startHFXT is called after PowerCC23X0_enterStandby.

static void PowerCC23X0_startHFXT(void)
{
    /* Only start HFXT if it is not already enabled. Trying to start the HFXT
     * if it is already enabled will cause TRACKREFLOSS when starting the LDO.
     * This situation can arise when:
     * - Waking up from fake standby. Fake standby does not shut down the HFXT,
     *   unlike real standby.
     * - Waking up without actually entering real standby. If a wakeup source is
     *   pending when we reach WFI in the ROM function, the hardware will just
     *   turn that into a NOP instead and not run through the regular state
     *   machine.
     */
    if ((HWREG(CKMD_BASE + CKMD_O_HFXTCTL) & CKMD_HFXTCTL_EN_M) != CKMD_HFXTCTL_EN)
    {
        /* Start LDO */
        HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_STARTCTL | CKMD_LDOCTL_START |
                                            CKMD_LDOCTL_EN);

        /* Bypass a lowpass filter that is connected to the reference voltage
         * for 66us to ensure that reference has settled.
         */
        HapiWaitUs(66);

        /* Clear START bits */
        HWREG(CKMD_BASE + CKMD_O_LDOCTL) = (CKMD_LDOCTL_SWOVR | CKMD_LDOCTL_HFXTLVLEN | CKMD_LDOCTL_EN);

        /* Force bias measurement before enabling HFXT - Set SRCSEL = BIAS.
         * Enable the peak detector in the HFXT amplitude control loop to
         * control RF phase jumps.
         */
        HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) = (CKMD_AMPADCCTL_SWOVR | CKMD_AMPADCCTL_PEAKDETEN_ENABLE |
                                               CKMD_AMPADCCTL_ADCEN_ENABLE);

        /* Delay to settle PEAKDET + ADC */
        HapiWaitUs(6);

        /* Clear raw interrupt for ADCBIASUPD */
        HWREG(CKMD_BASE + CKMD_O_ICLR) = CKMD_ICLR_ADCBIASUPD;

        /* Start an SAR conversion */
        HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) |= CKMD_AMPADCCTL_SARSTRT;

        /* Immediately prevent any SAR new conversions from starting. The one
         * started above will complete though.
         */
        HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~CKMD_AMPADCCTL_SARSTRT;

        /* Wait until HFXT-ADC BIAS measurement is done */
        while (!((HWREG(CKMD_BASE + CKMD_O_RIS) & CKMD_RIS_ADCBIASUPD_M) == CKMD_RIS_ADCBIASUPD)) {}

        /* Clear SW override of amplitude ADC */

        /* Keep PEAKDET on */
        HWREG(CKMD_BASE + CKMD_O_AMPADCCTL) &= ~(CKMD_AMPADCCTL_SWOVR_M | CKMD_AMPADCCTL_ADCEN_M);

        /* Start HFXT */
        HWREG(CKMD_BASE + CKMD_O_HFXTCTL) |= CKMD_HFXTCTL_EN;
    }

    /* Disallow standby until AMPSETTLED is true */
    Power_setConstraint(PowerLPF3_DISALLOW_STANDBY);

    /* Enable the AMPSETTLED interrupt.
     * Since it is a level status signal, it remains asserted when we are
     * running on HFXT and cannot be cleared.
     * The oscillator interrupt removes it from the interrupt mask to prevent
     * repeated vectoring.
     */
    HWREG(CKMD_BASE + CKMD_O_ICLR)  = CKMD_ICLR_AMPSETTLED;
    HWREG(CKMD_BASE + CKMD_O_IMSET) = CKMD_IMSET_AMPSETTLED;
}

When the J-link RTT debugger is connected, the device likely keeps the HFXT enabled in what is referred to as a "fake standby".  Thus there is no extra overhead after exiting standby in this case, so the overall delay is very similar to the Wakeup Timing parameter in the datasheet. With a free-running device, there are additional delays implemented in the Power TI Driver to safely start the HFXT, which will result in a longer time before ISRs are executed. 

As the UART hardware peripheral itself disables standby mode during UART RX functionality, you could stay in active mode always or use a dummy first byte to wake the device, disable standby, read the following UART bytes, and re-enable standby after a timeout or completed reading all bytes.

Regards,
Ryan