CC2340R5-Q1: Enable LF Loss Detection w/ external 32K Crystal

Hello,

What is the error that they are getting? Is the device just not resetting when this code is ran?

Best,

Nima Behmanesh

Hi Nima, 

The following is my customter's test result:

The current testing results show that placing the code at the beginning of the program and enabling custom MCUBoot signing causes the program to freeze.

However, moving the code to the end of the App_StackInitDoneHandler() function or using the root-ec-p256.pem signature file provided by TI resolves the issue.

Placing the code before App_StackInitDoneHandler() + root-ec-p256.pem ------ OK
Placing the code after App_StackInitDoneHandler() + custom .pem ------ OK
Placing the code before App_StackInitDoneHandler() + custom .pem ------ NG

Please help to provide comments.

Thanks.

Hello,

If they run the code before App_STackInitDoneHandler, but include it in a critical section do they still see it fail?

Best,

Nima Behmanesh

Hi Nima, 

Update the test result:

Base on the suggestion that you provide ,  my customer place the code before App_StackInitDoneHandler() + custom .pem,

the test result is still fail.

The following is the code:

Besides,  In the case "Placing the code after App_StackInitDoneHandler() + custom .pem ------ OK", 

my customer try this solution at production line last Friday, the found the pass rate is only 33%.

Please help to check the following question for my customer:

1. CC2340 TRM said:

　　　＂When the LF clock loss feature is enabled by setting the PMCTL.RSTCTL[2] LFLOSS bit and CKMD.LFMONCTL[0] EN bit＂

　 Can the register " PMCTL.RSTCTL[2] LFLOSS bit and CKMD.LFMONCTL[0] EN bit"  be controlled in the code? 

2.  Will system default enable LF clock loss feature ?

3. What is the right timing to enable/disable LF clock loss feature ?

Please help provide comments.

Thanks.

Hello,

Mike Wu1 said:

1. CC2340 TRM said:

　　　＂When the LF clock loss feature is enabled by setting the PMCTL.RSTCTL[2] LFLOSS bit and CKMD.LFMONCTL[0] EN bit＂

　 Can the register " PMCTL.RSTCTL[2] LFLOSS bit and CKMD.LFMONCTL[0] EN bit"  be controlled in the code? 

Yes, both of those are R/W, so they can be controlled in the code.

Mike Wu1 said:

2.  Will system default enable LF clock loss feature ?

Based on what I see in the TRM, no, the system will not default to enable:

You can see that it's set to 0 by default, so it's disabled.

Mike Wu1 said:

3. What is the right timing to enable/disable LF clock loss feature ?

The right timing to enable/disable the LF clock loss feature is after the LF clock source has been selected, is running (i.e. enabled) and is stable. This is from the above image of the register description.

Best,

Nima Behmanesh

Hi Nima,

Customer would like to know why they did not enable the LFMONITOR , but the SDK-provided API (PowerLPF3_getResetReason) reported LF clock loss as reset reason? 

Hi,

Are they calling PowerLPF3_selectLFOSC? If so, this function will enable the LFMONITOR. Based on the code I see, it seems the Power driver enables the LFMONITOR depending on whether the LFOSC is selected.

Best,

Nima Behmanesh

Hi Nima

Customer did not call PowerLPF3_selectLFOSC , any other suggestion that my customer can check to clarify why LF clock loss as a reset reason? Do you need review the source code ?

Hi,

One way is to attach a debugger and check the values of those registers that are needed to be set for it to be enabled. If those registers are set, then it will be enabled. I believe there is a way to set a breakpoint on these registers as well, in the case that they are modified a callstack can be generated to track down the functions that are enabling this feature.

Best,

Nima Behmanesh

Hi Nima

Is it correct we read these two register ? any other register we need to check also ?

PMCTL.RSTCTL[2] LFLOSS bit and CKMD.LFMONCTL[0] EN bit 

Hello,

Yes those two registers are the ones that should be read.

Best,

Nima Behmanesh