CC2340R5: 48MHz Crystal tuning

Hi,

Please see section 9 of this app note: https://www.ti.com/lit/pdf/swra495

Regards

Hello FI,

I understood #1 and #2-1. 

So remaining question is, #2-2 because this is not documented in Section 9.         

Q2-2)  Can we read and confirm this setting value after setting by sysconfig ?

Regards,

A.Fujinaka

Hello FI,

I have another question.

Q3.  9 Internal Capacitor Array for CC23XX and CC27XX, it describes Q1CAP range is 0 to 13pF, also Cpin = ~ 7pF.

For this case, total capacitance should be min. 7pF+ 0pF to max. 7pF + 13pF for each X48P and X48N because capacitor is put in parallel. Am I wrong?

Q4: What is the default value of Q1CAP and Q2CAP?

Regards,

A.Fujinaka

Hi,

Q3: you are right.
Q4: default value, looking from SW, is 35 (6.6pF from table)

Hello FI,

Regarding Q3, I can not understand the followings.

1) The figure shows Q1CAP = 0 -13pF, Q2CAP = 0 -13pF ,respectively.

2) The list shows Q1= Q2 , min. (1) = 3.7pF,  max (61) = 9.9pF.

3) Limitation says,

If external load capacitors are used, then TI recommends to set Q1CAP and Q2CAP to 0 in the syscfg file.

This results in an estimated total parasitic capacitance of approximately 3-4pF

-> You said, 7pF is min. how it achieve 3-4pF in total?

Which is correct?

Regards,

A.Fujinaka

Hi,

The two 7pF pin capacitor are in series which will present 7 / 2 = 3.5pF to the xtal.

regards

Hello 

1)  If the connection is like bellow, it is series, the total capacitance is 3.5uF.

But  for this case, it is parallel, am I wrong?

2)  Q2-2)  Can we read and confirm this Q1= Q2 setting value after setting by sysconfig ?

Regards,

A.Fujinaka

Hi,

1) it is in series w.r.t to the crystal. See section 3.3 of https://www.ti.com/lit/pdf/swra495

2) You can read the value from the fields of following registers CKMD.HFXTINIT.Q2CAP
 see TRM section 6.9.34 HFXTINIT Register