should I care about the FCTL full bit in addition to the busy bit when polling the FCTL register to see if the flash write has completed?
sample code does not care, but the full bit as well as the busy bit is definitely being set in the polling after the DMA is triggered to flash. I am configuring the DMA's via the debug interface.
FCTL (0x6270) – Flash Control
|
Bit |
Name |
Reset |
R/W |
Description |
|
7 |
BUSY |
0 |
R |
Indicates that write or erase is in operation. This flag is set when the WRITE or ERASE bit is set. 0: No write or erase operation active 1: Write or erase operation activated |
|
6 |
FULL |
R/H0 |
Write buffer-full status. This flag is set when 4 bytes have been written to FWDATA during flash write. The write buffer is then full and does not accept more data; that is, writes to FWDATA are ignored when the FULL flag is set. The FULL flag is cleared when the write buffer again is ready to receive 4 more bytes. This flag is only needed when the CPU is used to write to the flash. 0: Write buffer can accept more data. 1: Write buffer full |
|
|
5 |
ABORT |
0 |
R/H0 |
Abort status. This bit is set when a write operation or page erase is aborted. An operation is aborted when the page accessed is locked. The abort bit is cleared when a write or page erase is started. |
|
4 |
– |
0 |
R |
Reserved |
|
3:2 |
CM[1:0] |
01 |
R/W |
Cache mode Cache mode. Disabling the cache increases the power consumption and reduces performance. Prefetching, for most applications, improves performance by up to 33% at the expense of potentially increased power consumption. Real-time mode provides predictable flash-read access time; the execution time is equal to that in cache-disabled mode, but the power consumption is lower. Note: The value read always represents the current cache mode. Writing a new cache mode starts a cache mode-change request that may take several clock cycles to complete. Writing to this register is ignored if there is a current cache-change request in progress. |
|
1 |
WRITE |
0 |
R/W1/ H0 |
Write. Start writing word at location given by FADDRH:FADDRL. The WRITE bit stays at 1 until the write completes. The clearing of this bit indicates that the erase has completed, that is, it has timed out or aborted. If ERASE is also set to 1, a page erase of the whole page addressed by FADDRH[7:1] is performed before the write. Setting WRITE to 1 when ERASE is 1 has no effect. |
|
0 |
ERASE |
0 |
R/W1/ H0 |
|
