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CC2564B 22kHz PCM FrameSync frequency

Martijn Broens
Prodigy 205 points

Hello,

for our application we are using the CC2564B in combination with dotstack. we have SPP running as well as assited A2DP sink but default the CC2564B outputs the PCM framesync at 44kHz. our codec does not take this frequency it takes 22kHz. How can we configure the SBC to output 22kHz???

at the wiki it table HCI_VS_Write_CODEC_Config (0xFD06) states the following:

Frame-sync frequency 4 100 Hz – 173 kHz Frame-sync frequency in Hz

Fsynch Multiplier

 1


0x00/0xFF 

32/64

 This feild is only relvant to CC256XB from SP 0.2 !!!

When setting the values 0x00 or 0xFF the command will act the same as previously, but when entering a value of 32/64 the Clock Rate will be: Clock Rate = Fsynch Multiplier X Frame Synch frequnecy , for example 44,100Hz X 32 = 1441,200Hz   

and

PCM input sample 1 0x1 – 0x9 The PCM sample frequency rate of the input PCM bus. This parameter is valid only when the audio source is the host. When this parameter is different from the SBC input sample frequency parameter the SARC will be used for sample rate conversion.
0x01 – 8000 Hz
0x02 – 11025 Hz
0x03 – 12000 Hz
0x04 – 16000 Hz
0x05 – 22050 Hz
0x06 – 24000 Hz
0x07 – 32000 Hz
0x08 – 44100 Hz
0x09 – 48000 Hz
SBC input sample frequency 1 0x0 - 0x3 The sample frequency rate of the PCM input to SBC encoder. Note that when this parameter is different from the PCM input sample frequency, the SARC is used for sample rate conversion.
0x0 – 16000 Hz
0x1 – 32000 Hz
0x2 – 44100 Hz
0x3 – 48000 Hz

at the moment we set the SBC Input sample freq to 0x02. (default) but we require 22kHz as mentioned

How can we setup the SBC for 22kHz framesync??

is there more documentation availeble on the multiplier?? the explanation above does not explain in full.

please advice.

btw: hardware is currently in production and will be received in 3 days from now our goal is to present the firts samples with the CC2564MODNCMOET at MWC in march so we are on a tight schedule

M.Broens

mBedit

  • 0
    TI__Mastermind 23565 points

    Hi,

    For Assisted A2DP mode, we only support 16KHz, 44.1KHz aand 48KHz at both SBC coding and PCM interface. Note that SBC Frequency MUST be equal to PCM frequency.

    http://www.ti.com/product/CC2564MODN/datasheet/detailed_description#swrs121564 - Table 5-6

    BTW, 22KHz is not an standard sampling rate. Which is your peer device?

    Regards,

    Miguel

  • 0 in reply to Miguel
    Prodigy 205 points

    Hi Miguel ,

    Than what does the satasheet mean with the freq ranges mentioned?

    Is there any way to power the framesync? This has just become a showstopper  for us.

  • 0 in reply to Miguel
    Prodigy 205 points

    Hi Miguel,

    22kHz is half cd rate. and the codec we interface to only supports this frame rate. we did not see this as an issue since the wiki states:

    HCI_VS_Write_CODEC_Config (0xFD06)

    Description:

    This command configures the codec interface parameters and the PCM clock rate, which is relevant when
    the Bluetooth core generates the clock. This command must be used by the host to use the PCM
    interface.

    Command Parameters:

    HCI_VS_Write_CODEC_Config (0xFD06) Clock rate, Clock direction, Frame-sync frequency, Frame-sync duty cycle, Frame-sync edge, Frame-sync polarity, Reserved, Channel 1 data out size,  Channel 1 data out offset,  Channel 1 data out edge, Channel 1 data in size, Channel 1 data in offset, Channel 1 data in edge, Reserved, Channel 2 data out size, Channel 2 data out offset, Channel 2 data out edge, Channel 2 data in size, Channel 2 data in offset, Channel 2 data in edge, Reserved

    Command ParameterSize (bytes)ValueDescription
    Clock rate 2 64-16,000 The PCM clock rate is between 64k to 4096k (for master mode) or 64K to 16M (for slave mode). It influences other parameters such as wait cycles and frequency rate calculation and therefore must be configured even if an external clock is used.
    Clock direction 1

    0x00

    0x01

    PCM clock and Fsync direction is output (codec_IF is Master on PCM bus) and sampled on rising edge

    PCM clock and Fsync direction is input
    Frame-sync frequency 4 100 Hz – 173 kHz Frame-sync frequency in Hz
    Frame-sync duty cycle 2


    0x0000

    0x0001-0xFFFF

    50% of Fsync period (I2S Format)

    Number of cycles of PCM clock

    and 22 is that range.

    From your statement i now understand that this is not correct. we are only able to output 44 and 16. or is there still an other way to achieve this??

    you mention that sbc frequency and PCM freq must be equal. where can i find more info on that? what are the ranges for both. in other words who's the limiting factor??

    kind regards,

    Martijn

  • 0 in reply to Martijn Broens
    TI__Mastermind 23565 points

    Hi Martijn,

    These are part of the BT A2DP specifications. This information is noted in our datasheet in the A3DP section.

    Which is your peer device?

    Regards,

    Miguel