Is modifying the cap array delta in the CCFG supported currently? It looks like by default the LF SLCK is the external 32.768Khz clock, which is what I want.
I am outputing the signal on a line using AONIOC32kHzOutputEnable. Measuring this line, I am seeing a pretty larger error: 140ppm.
I read in the data sheet that the cap array delta for XOSC can be modified, but in code (CCFG) it says it may not be supported. Is this true? I ask because I am enabling the use of the delta, and setting the delta to various values and the frequency counter reading does not change.
Thanks,
Ben