GPTimers Edge Time 24bit/16bit Errors in the Ref. Manual

I have configured GPT0 timerA in edge time mode, which per the TRM is a 24bit counter with the time of the last edge stored in TAR register (LSB 16bits) and the TAPR (MSB 8 bits) - aka the prescale register should hold the upper bits (pg1119 and others)

What actually occurs in practice is much different, firstly, if the TAPR register is initially set to 0 (prescale ratio of 1) , the TAPR register remains 0 always ( no matter if the TAR value wraps over 0x0000FFFF. Additionally, the TAPS/TAPV registers also remain 0.

Now, if you write the TAPR register with a value of 255 (0xFF) some more interesting things happen:

The TAPR register will remain at the value of 0xFF ( which makes me think it is only for setting values and has nothing to do with readback) however the registers TAPS and TAPV now contain 8bit values that ARE changing with each edge time. Here is an example,

TAR = 0x00328D7B (time of last edge)

TAV = 0x00328F9D (current timer value)

TAPS = 0x00000032 

TAPV = 0x00000032

So I think I now have 24 bit mode operating, although it's interesting it seems the 24bits are all contained in TAR.. Additionally, I don't know exactly what setting the TAPR to 255 really accomplished. 

I hope TI can remedy the confusion on this topic, it seems I am not alone: 

Here is my code: 

  Power_setDependency(PERIPH_GPT0); // Power up Periph/clock for GPT0
  Power_setConstraint(Power_SB_DISALLOW); //while running dont power down 
  PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
  PRCMLoadSet();
  PRCMPeripheralRunEnable(PRCM_PERIPH_TIMER0);
  PRCMLoadSet();
  //set pinmux for IOD6 to event0
  PINCC26XX_setMux(hPins,IOID_6,IOC_PORT_MCU_PORT_EVENT0);
  //clear timer regs
  HWREG(GPT0_BASE + GPT_O_CTL) = 0;
  HWREG(GPT0_BASE + GPT_O_TAMR) = 0;
  HWREG(GPT0_BASE + GPT_O_TAPR) = 0;
  HWREG(GPT0_BASE + GPT_O_TBPR) = 0;
  HWREG(GPT0_BASE + GPT_O_TBMR) = 0;
  HWREG(GPT0_BASE + GPT_O_CFG) = 0x00000004; //timers in 16bit mode

  HWREG(EVENT_BASE + EVENT_O_GPT0ACAPTSEL) = EVENT_GPT0ACAPTSEL_EV_PORT_EVENT0;
  TimerPrescaleSet(GPT0_BASE, TIMER_A, 255);

  TimerConfigure(GPT0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_CAP_TIME_UP);
  TimerEventControl(GPT0_BASE,TIMER_A,TIMER_EVENT_POS_EDGE);
  TimerWaitOnTriggerControl(GPT0_BASE, TIMER_A, FALSE);
  TimerStallControl(GPT0_BASE,TIMER_BOTH,TRUE);