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CC2564B TLV320AIC3100 ASSISTED MODE

Paolo Martinetti
Expert 2730 points

Other Parts Discussed in Thread: TLV320AIC3100, CC256XSTBTBLESW

Hi,

I use stm32f4, CC2564B and TLV320AIC3100 in assisted mode. CC2564B is I2S Master, codec slave.

I'm not able to setup a Service Level Connection with my Android phone. (I open a remote handsfree port using bluetopia stack, but after the confirmation, there is no SLC indication). What should I do?

The codec not correctly configured may be the cause?

Thanks in advance,

Paolo

  • 0
    TI__Mastermind 20285 points
    Hi,
    Your query has been assigned to the relevant expert.
    Please expect a followup response.
    BR,
    Eyal
  • 0
    TI__Mastermind 29361 points
    Hi Paolo,

    Are you using the HFPDemo_HF.c as it is in the CC256XSTBTBLESW SDK? If not what changes have you made? Are you following the steps in the demo guide wiki?
    processors.wiki.ti.com/.../CC256x_STM32_TI_Bluetooth_Stack_HFPDemo_App

    You are correct that it could be a problem in the audio codec initialization, but I want to make sure we are not missing anything else.


    Best regards,
    VIhang
  • 0 in reply to Vihang Parmar
    Expert 2730 points

    Hi VIhang,

    i changed the file HFPDemo.c a lot, because i Use CC2564B and TLV320AIC3100 in HFP assisted mode.

    In my code I initialize the audio without any Service Level Connection opened. TLV codec is BCLK and WCLK Master:

    init_I2C1();              // Init i2c
    hw_reset_codec(); // reset Codec via GPIO
    initialize_codec(); /     

    VS_PCM_Codec_Config_Slave_I2S(BluetoothStackID, I2S_CLK_FREQ_IN_FS_16KHZ, 16000);

    initialize_codec() does the following initializations:

    write_reg(I2C1,0,0x00); // page 0
    write_reg(I2C1,1,0); // initiate sw reset
    BTPS_Delay(2); // wait 2 msec
    write_reg(I2C1,3,0x02); // over temperature protection -> normal operation
    write_reg(I2C1,53,0x00); // DOUT (OUT Pin) Control
    write_reg(I2C1,54,0x02); // DIN (IN Pin) Control

    write_reg(I2C1,27,0x0c); // Codec Interface Control I2S, word 16 bit, BCLK output, WCLK output, DOUT High Imp. disabled
    write_reg(I2C1,29,0x01); // BDIV_CLKIN = DAC_MOD_CLK
    write_reg(I2C1,30,0x01); // BDIV_N_VAL = 16
    write_reg(I2C1,4,0x03); // clock generation muxing -> PLL_CLKIN = MCLK, CODEC_CLKIN = PLL_CLK
    write_reg(I2C1,5,0xd3); // PLL P = Power up, divider 5 , R = 1 (multiplier) (ex d1)
    BTPS_Delay(15);
    write_reg(I2C1,6,0x00); // PLL multiplier J =0
    write_reg(I2C1,7,0x00); // PLL D-Value MSB 0
    write_reg(I2C1,8,0x00); // PLL D-Value LSB 0
    write_reg(I2C1,11,0x85); // DAC NDAC power up, divider 5
    write_reg(I2C1,12,0x8a); // DAC MDAC power up, divider 10
    write_reg(I2C1,14,0x80); // DOSR 128
    write_reg(I2C1,60,0x06); // DAC Instruction Set PRB_P6

    write_reg(I2C1,0,0x01); // page 1
    write_reg(I2C1,34,0x70); // Output Driver PGA Ramp_Down Period Control
    write_reg(I2C1,32,0x86); // Class-D Speaker
    write_reg(I2C1,42,0x04); // SPK Driver
    write_reg(I2C1,38,0xFF); // Left Volume --> SPK
    write_reg(I2C1,35,0x40); // DAC_L and DAC_R routed to mixer
    write_reg(I2C1,0,0x00); // page 0
    write_reg(I2C1,63,0x94); // DAC DP SETUP
    write_reg(I2C1,64,0x04); // DAC VOLUME CONTROL

    write_reg(I2C1,0,0x01); // page 1
    write_reg(I2C1,38,0x80); // Left Volume --> SPK