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CC2640: I2S

Part Number: CC2640
Other Parts Discussed in Thread: TLV320AIC3120

I am not finding software support for I2S read mode from master(i,e CC2640 ). Please show me the way ,How i can use I2S protocol , to read the data from audio Codec (i,e TLV320aic3120) . I am using BLE stack 2.2 for programming reference .

  • Hi,

    We are working on making a example for exactly what you want. It will take couple of weeks till it's ready on our github :

    For now, you can try to use our pdm driver in TI-RTOS(PDMCC26XX_util.c) and then modify the parameters to whatever you need.

        /* Initialize the I2S object */
        object->requestMode                 = params->requestMode;
        object->ui32requestTimeout          = params->ui32requestTimeout;
        object->blockSize                   = params->blockSize;
        object->pvContBuffer                = params->pvContBuffer;
        object->ui32conBufTotalSize         = params->ui32conBufTotalSize;
        object->pvContMgtBuffer             = params->pvContMgtBuffer;
        object->ui32conMgtBufTotalSize      = params->ui32conMgtBufTotalSize;
        object->currentStream               = params->currentStream;
        object->currentStream->status       = PDMCC26XX_I2S_STREAM_IDLE;
    
        /* The following are constants that apply to PDM */
        object->i32SampleRate = -1;                                                  /* If negative then use user configured clock division */
        object->audioClkCfg.wclkDiv = 16;                                            /* I2S Word Clock divider override*/
        object->audioClkCfg.sampleOnPositiveEdge = PDMCC26XX_I2S_SampleEdge_Postive; /* I2S Sample Edge */
        object->audioClkCfg.wclkPhase = PDMCC26XX_I2S_WordClockPhase_Dual;           /* I2S Word Clock Phase */
        object->audioClkCfg.wclkInverted = PDMCC26XX_I2S_ClockSource_Normal;         /* I2S Invert Word Clock */
        object->audioClkCfg.wclkSource = PDMCC26XX_I2S_WordClockSource_Int;          /* I2S Word Clock source */
        object->audioClkCfg.bclkDiv = 47;                                            /* I2S Bit Clock divider override */
        object->audioClkCfg.reserved = 0;
        object->audioClkCfg.bclkSource = PDMCC26XX_I2S_BitClockSource_Int;           /* I2S Bit Clock source */
        object->audioClkCfg.mclkDiv = 6;                                             /* I2S Master Clock divider override */
    
        object->audioPinCfg.bitFields.ad1Usage = PDMCC26XX_I2S_ADUsageDisabled;      /* I2S AD1 usage (0: Disabled, 1: Input, 2: Output) */
        object->audioPinCfg.bitFields.enableMclkPin = PDMCC26XX_I2S_GENERIC_DISABLED;/* I2S Enable Master clock output on pin */
        object->audioPinCfg.bitFields.reserved = 0;
        object->audioPinCfg.bitFields.ad1NumOfChannels = 0;                          /* I2S AD1 number of channels (1 - 8). !Must match channel mask */
        object->audioPinCfg.bitFields.ad1ChannelMask = PDMCC26XX_I2S_DISABLED_MODE;  /* I2S AD1 Channel Mask */
        object->audioPinCfg.bitFields.ad0Usage = PDMCC26XX_I2S_ADUsageInput;         /* I2S AD0 usage (0: Disabled, 1: Input, 2: Output) */
        object->audioPinCfg.bitFields.enableWclkPin = PDMCC26XX_I2S_GENERIC_DISABLED;/* I2S Enable Word clock output on pin */
        object->audioPinCfg.bitFields.enableBclkPin = PDMCC26XX_I2S_GENERIC_ENABLED; /* I2S Enable Bit clock output on pin */
        object->audioPinCfg.bitFields.ad0NumOfChannels = 2;                          /* I2S AD0 number of channels (1 - 8). !Must match channel mask. \sa PDM_NUM_OF_CHANNELS */
        object->audioPinCfg.bitFields.ad0ChannelMask = PDMCC26XX_I2S_STEREO_MODE;    /* I2S AD0 Channel Mask */
    
        object->audioFmtCfg.wordLength = PDMCC26XX_I2S_WordLength16;                 /* Number of bits per word (8-24). Exact for single phase, max for dual phase */
        object->audioFmtCfg.sampleEdge = PDMCC26XX_I2S_PositiveEdge;                 /* Data and Word clock is samples, and clocked out, on opposite edges of BCLK */
        object->audioFmtCfg.dualPhase = PDMCC26XX_I2S_SinglePhase;                   /* Selects dual- or single phase format (0: Single, 1: Dual) */
        object->audioFmtCfg.memLen = PDMCC26XX_I2S_MemLen16bit;                      /* Size of each word stored to or loaded from memory (0: 16, 1: 24) */
        object->audioFmtCfg.dataDelay = PDMCC26XX_I2S_FormatLJF;                     /* Number of BCLK perids between a WCLK edge and MSB of the first word in a phase */

  • HI Christin Lee,

    I was also working on the same, but i din got how to configure and use the code given in Github, can u please help me on this, 

  • Hi Christin ,

    Can i generate clock from master i,e from CC2640 by using PDM driver? ,Its not understanding from me . I could not Generate master clock and word clock. please help me out. I can say i am new to I2S. Please help me out for beginners.

  • As long as you initialize the driver, the driver will take care of the clock setting and configure the device to generate the clk.
    I am not sure what you meant by you can't generate master clock...etc
  • Thank you christlie for ur response , Sorry my understand gone wrong. From Codec I am getting BLCK,DOUT output. I observed in CRO .I planning to capture the data from CC2640,let me see how these driver help me out. I will go in detail , and i will ping you back , If i need help .
  • Hi christin,

           Any update on above topic,Can we get I2S driver in deoxygen ?

  • The github example should be available in a week or two. We are waiting for the release to be approved now.
    By then, you can just check the example to see how to use I2S.
    We currently don't have I2S doxygen.