Part Number: CC2650STK
Other Parts Discussed in Thread: BLE-STACK
Tool/software: TI-RTOS
Hi,
In the ref file for PDMCC26xx.h, there is "This driver is configured to process 256 bytes of PDM data provided by the I2S hardware module at a time, sampled at 1.024 Mbps" and "The application must allow for the PDM driver task to run often enough to process the data received from I2S driver approximately every 2ms".
Now I would like to receive PDM data approximately every 5ms or more because I want the program to do more while waiting for a new PDM buffer.
I found the following code in PDMCC26xx_util.c, I think they are related to I2S sampling rate.
/* The following are constants that apply to PDM */ object->i32SampleRate = -1; /* If negative then use user configured clock division */ object->audioClkCfg.wclkDiv = 16; /* I2S Word Clock divider override*/ object->audioClkCfg.sampleOnPositiveEdge = PDMCC26XX_I2S_SampleEdge_Postive; /* I2S Sample Edge */ object->audioClkCfg.wclkPhase = PDMCC26XX_I2S_WordClockPhase_Dual; /* I2S Word Clock Phase */ object->audioClkCfg.wclkInverted = PDMCC26XX_I2S_ClockSource_Normal; /* I2S Invert Word Clock */ object->audioClkCfg.wclkSource = PDMCC26XX_I2S_WordClockSource_Int; /* I2S Word Clock source */ object->audioClkCfg.bclkDiv = 15; /* I2S Bit Clock divider override */ object->audioClkCfg.reserved = 0; object->audioClkCfg.bclkSource = PDMCC26XX_I2S_BitClockSource_Int; /* I2S Bit Clock source */ object->audioClkCfg.mclkDiv = 6; /* I2S Master Clock divider override */
In the past I have already changed the audioClkCfg.bclkDiv in order to increase the PCM data sampling rate, if I want to decrease the 1.024 Mbps in order to receiver a PDM data buffer for longer time, which parameter should I change? (are there any side effects of doing this?)
Thank you in advance