I’m looking at how the SPI driver behaves on the CC2640R2, specifically with how the Chip Select (CS) pin functions. It looks like the device is capable of controlling the CS via hardware, as well as allowing the application to control via software. I was reading through the SPI.h file and saw the following excerpt and wanted to confirm some questions I have.
* <h2><a NAME="Master_Slave_Modes">Master/Slave Modes</a></h2>
* This SPI driver functions in both SPI master and SPI slave modes.
* Logically, the implementation is identical, however the difference between
* these two modes is driven by hardware. As a SPI master, the peripheral is
* in control of the clock signal and therefore will commence communications
* to the SPI slave immediately. As a SPI slave, the SPI driver prepares
* the peripheral to transmit and receive data in a way such that the
* peripheral is ready to transfer data when the SPI master initiates a
* transaction.
*
* ### Asserting on Chip Select
* The SPI protocol requires that the SPI master asserts a SPI slave's chip
* select pin prior to starting a SPI transaction. While this protocol is
* generally followed, various types of SPI peripherals have different
* timing requirements as to when and for how long the chip select pin must
* remain asserted for a SPI transaction.
*
* Commonly, the SPI master uses a hardware chip select to assert and
* de-assert the SPI slave for every data frame. In other cases, a SPI slave
* imposes the requirement of asserting the chip select over several SPI
* data frames. This is generally accomplished by using a regular,
* general-purpose output pin. Due to the complexity of such SPI peripheral
* implementations, this SPI driver has been designed to operate
* transparently to the SPI chip select. When the hardware chip
* select is used, the peripheral automatically selects/enables the
* peripheral. When using a software chip select, the application needs to
* handle the proper chip select and pin configuration. Chip select support
* will vary per SPI peripheral, refer to the device specific implementation
* documentation for details on chip select support.
*
* - _Hardware chip select_ No additional action by the application is
* required.
* - _Software chip select_ The application needs to handle the chip select
* assertion and de-assertion for the proper SPI peripheral.
- What is meant by “When the SPI master initiates a transaction” when the device is in SPI slave mode? Does initiates a transaction mean a CLK signal begins on the CLK line or does this involve the CS going low?
- When the device is in SPI slave mode, what’s the behavior of the hardware chip select? Is there a chip select?
- Does “this SPI driver has been designed to operate transparently to the SPI chips select” mean the CS line essentially ignored regardless if device is setup as SPI master or slave?
-
- For example, in SPI slave mode, if a CLK signal is present on the CLK line, data would exit the Tx buffer/be read into the Rx buffer regardless of the CS? Or would it need to acknowledge CS being active low before data would enter/leave Tx/Rx buffers?
- What’s the procedure for switching between hardware chip select and software chip select? Is it as simple as defining the CS pin to be PIN_UNASSIGNED to disable the hardware chip select?
