CC2560: Acceptable Clock SBC Encoder/Decoder

Ajay Wong

Prodigy 100 points

Part Number: CC2560

I am using the CC2560 assisted Mode.

I would know about the technical parameter for the SBC encoder/decoder firmware in the TI Chps.

My FSync is data expected to run at the 48kHz, but my hardware may be some tolerance in the crystal.

I would like to check, what is the acceptable range for the tolerance, such that the SBC encoder/decoder can accept?

Say, if my clock as at 47.9kHz, or 48.1kHz. I want to know if there is such acceptable range for the clock defined?

If, the clock in some case, the clock is out of the scope, what will the encoder/decoder firmware handle? Will it still work with some jitter, or it will do some adaption, or just discard all the input data?

over 7 years ago

0 Chen Loewy over 7 years ago

TI__Expert 5285 points

Hello Ajay,

The less accurate your clock is the more jitter will be which might cause overruns/underruns which might results by ticks from time to time if it's very close like you describe here or distortion if the clock isn't accurate at all.

BR,
Chen Loewy

0 Ajay Wong over 7 years ago in reply to Chen Loewy

Prodigy 100 points

So, how much tolerance there?

As we may not able to generate exactly 48kHz.

0 Chen Loewy over 7 years ago in reply to Ajay Wong

TI__Expert 5285 points

Hi,

You can let the CC2560 be the master on the PCM - hence it will generate the clock from it's fast clock.

Did you look at the following Wiki pages?
processors.wiki.ti.com/.../CC256x_VS_HCI_Commands
processors.wiki.ti.com/.../CC256x_System_Design_Guide

BR,
Chen Loewy

0 Ajay Wong over 7 years ago in reply to Chen Loewy

Prodigy 100 points

Hi Chen Loewy,

As cannot config the Audio source much, so we may need to stick with the PCM Slave.

Do we have a tolerance value there?

regards,
Ajay

0 Vihang Parmar over 7 years ago in reply to Ajay Wong

TI__Mastermind 29291 points

Hi Ajay,

Please refer to the following e2e thread about the same topic:
e2e.ti.com/.../678214

To answer your question, the FSync signal has 0% tolerance with respect to the network clock of the BT connection. This is an implied tolerance value from the BT spec, so the CC256x does not need to list it separately.

When your FSync is inaccurate, you are risking PCM overrun or underrun depending on the clock drift of your BT connection. These overruns or underruns will result in glitches or noise as mentioned by Chen above. If you make the CC256x PCM master and the master of the BT connection, both the PCM clocks and the BT network clocks will be driven by the same source (fast clock signal of the CC256x). This will ensure that there is no clock drifts between BT and PCM interfaces. With any other combination (i.e. CC256x as PCM slave), you are risking the PCM overrun or underrun.

Best regards,
Vihang

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CC2560: Acceptable Clock SBC Encoder/Decoder