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SIMPLELINK-CC26X2-SDK: How to configure the I2S clock for CC2642

Trevor Hsu
Genius 4585 points

Part Number: SIMPLELINK-CC26X2-SDK

we would like to connect with external audio codec for CC2642.

we have found the I2S driver source on github()

    object->i32SampleRate = 0; // I2S_SAMPLE_RATE_48K;                       /* If negative then use user configured clock division */
    object->audioClkCfg.wclkDiv = 250; //16                                  /* I2S Word Clock divider override*/
    object->audioClkCfg.sampleOnPositiveEdge = I2SCC26XX_SampleEdge_Postive; /* I2S Sample Edge */
    object->audioClkCfg.wclkPhase = I2SCC26XX_WordClockPhase_Dual;           /* I2S Word Clock Phase */
    object->audioClkCfg.wclkInverted = I2SCC26XX_ClockSource_Normal;         /* I2S Invert Word Clock */
    object->audioClkCfg.wclkSource = I2SCC26XX_WordClockSource_Int;          /* I2S Word Clock source */
    object->audioClkCfg.bclkDiv = 6;//94;                                    /* I2S Bit Clock divider override */
    object->audioClkCfg.reserved = 0;
    object->audioClkCfg.bclkSource = I2SCC26XX_BitClockSource_Int;           /* I2S Bit Clock source */
    object->audioClkCfg.mclkDiv = 4;                                         /* I2S Master Clock divider override */

Regarding the I2S clock setting, the default setting is 16KHz sample rate. but we need the 48Khz sample rate, do you know how to modify the wclkDiv, bclkDiv and mclkDiv?

  • 0
    TI__Guru**** 317180 points
    That will depend a bit on what the codec expects.
    - Does the codec derive the it's clocks from BCLK or MCLK?

    wclkdiv needs to be set so 48 MHz/ wclkdiv is closest possible to 48 kHz.

    bclkdiv is dependent on which frequency you need on BCLK. If you use 16 bit, bclk will be 16x2*wclk or possible 17*2*wclk dependent on the I2S format (See the codec and driver documentation on which pulse the first bit is clocked if 16 or 17 pulses are needed to clock out)
  • 0 in reply to TER
    Genius 4585 points
    Got it, thanks.
    some questions need your help:
    1.
    In your example code, the cc26x2 is connected to AIC3254 and AIC3254 input clock is configured to BCLK.
    if we would like change to 48K sample rate, how to modify the wclkDiv, bclkDiv and mclkDiv?
    2.
    we have the another audio codec(ALC5640), the input clock is MCLK and the MCLK is set to 256fs(256*48000), WCLK is 48KHz, BCLK is 3.072MHz (64FS).
    could you help to provide the configuration of wclkDiv, bclkDiv and mclkDiv?
  • 0 in reply to Trevor Hsu
    TI__Guru**** 317180 points
    We can help on where in the driver you need to change the wclkDiv, bclkDiv and mclkDiv but we are not able to provide the exact numbers for a given setup.

    For question 1 I suggested a starting point for wclkdiv and bclkdiv. MCLK is dependent on how you set up the codec and which frequency you want to run this on. For the examples on github, bclk is used by the codec and mclk is shorted to bclk on the boosterpack used. But in some cases mclk should be used as the main clock on the codec, dependent on which limitations and ranges of valid clocks the codec accepts.
  • 0 in reply to TER
    Genius 4585 points

    I know that I have to modify  these clock division, but I don't know how to modify them.

    Regarding the following division values, could you help to provide the some descriptions?

    object->audioClkCfg.wclkDiv = 250;

    object->audioClkCfg.bclkDiv = 6;

    object->audioClkCfg.mclkDiv = 4;                                      

  • 0 in reply to Trevor Hsu
    TI__Guru**** 317180 points
    Not sure if I understand your question: Do you need to know how you modify the number (write something else at the end of the lines) or what you should modify them to?
  • 0 in reply to TER
    Genius 4585 points
    For example, in your example code, the audio codec is configured to 16KHz, so CC2642's WCLK need to output a 16KHz clock and configure wclkDiv = 250 to reach the 16KHz frequency.
  • 0 in reply to Trevor Hsu
    Genius 4585 points
    do you understand my question???
    thanks.
  • 0 in reply to Trevor Hsu
    TI__Guru**** 317180 points
    Not sure if I saw a question, your last post (from 12:23 am) looks more like a statement.

    I'm not familiar with the driver in the github example since this is a alpha release. A new I2S driver will be released in the Q1 release of the SDKs and we will therefore provide limited support related to the alpha version.

    If you look at the equations in the TRM (www.ti.com/.../swcu117h.pdf, page 1546):
    WCLK = MCUCLK / {BDIV × (2 × WDIV[9:0])}

    If you put in the numbers: MCUCLK = 48e6, WDIV = 250 gives WCLK = 16000

    Basically you have to look at the equations given on page 1546 and see which division factor you have to use in your case.
  • 0 in reply to TER
    Genius 4585 points

    Okay, thanks for your information.