Other Parts Discussed in Thread: CC2541, CC2640,
On the CC2640R2, it looks like the SPI peripheral has different behavior in slave mode depending on the clock phase setting. In SPH=0, it expects a FSS pulse in between each word, however in SPH=1 it expects the FSS to be asserted (low) during the entire multi-byte transfer. The SPH=1 behavior for FSS is what is expected, however a previous design using the CC2541 did not have the same restriction (i.e. it uses SPH=0 and SPL=0 without the FSS pulse). The attempt here is to use a CC2640 module as a drop-in replacement for the existing CC2541 design.
Is there any way to control the behavior of the SPI peripheral such that the SPH bit does not lock the data register contents?
Regards,
Michael
