CC2642R: Maximum SPI Speed in Master mode without DMA

Oliver Maier

Part Number: CC2642R

Hello,

I want to transfer image data from an external serial Flash to a small LCD display with a serial interface and an internal framebuffer.

In the technical document SWRS194C the maximum SSI clk cycle time is limited to 12 System Clocks which is only 4 Mbps.

I have successfully tested bitrates of up to 24MHz without DMA and as a SPI Master for both SPI read from the external flash and SPI write to the display framebuffer.

My question is, if the slow 4 Mbps clock is really the guaranteed technical limit under my restrictions (SPI Master, no DMA).

Thank You for Your support!

Kind regards

Oliver

over 6 years ago

0 Seong Kim over 6 years ago

TI__Mastermind 46531 points

Hi Oliver,

Please see this related post: e2e.ti.com/.../2143931

BR,
Seong

0 Oliver Maier over 6 years ago in reply to Seong Kim

Prodigy 50 points

Hello Seong,

Thank you for your reply!

12Mbps is much better than 4Mbps, but is this limit caused by the capabilities of the UDMA controller or is it a SPI hardware restriction (errors caused by overclocking)?

Instead of using the TI SPI driver implementation I do direct hardware register programming to gain the maximum performance. The UDMA transfer was not useful for me because of RLE of my image data and 9-Bit transfers to the display hardware with a fixed first Bit.

Kind regards

Oliver

0 Fredrik K over 6 years ago in reply to Oliver Maier

TI__Guru** 106705 points

Hi Olivier,

The limitation is HW-associated, more specifically limited by the frequency capability IO pins. You can probably push the HW beyond the datasheet limits, but it is not something we can stand behind in terms of guaranteeing operation over conditions, etc.

Regards,
Fredrik

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CC2642R: Maximum SPI Speed in Master mode without DMA