Team,
The comment below describes setting the tuning caps to zero to reduce the 48MHz spurs, can you confirm if this means 0pF (with the internal array disabled -40 value) or a zero value in the CCFG register?
CC2652 there will be spurs at N x 48 MHz offset from the carrier. These spurs are caused by the current going back and forth between the crystal and the XOSC tuning capacitors (which form the oscillator tank together with off-chip capacitances). This current is quite large due to the high Q of the crystal tank and will create an IR drop on the power rails that are shared with the PA and VCO. Setting the XOSC tuning capacitors to zero reduces the spurs by approximately 5 dB for the largest spur compared to the default setting. The internal capacitor array can be used in most use cases, but it is recommended to use external crystal loading capacitors and setting the internal XOSC tuning capacitors to zero for systems targeting compliance with ARIB STD T-108 and Chinese regulations in 470 – 510 MHz frequency band as well as when using the +20 dBm PA.
Thanks
