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CC2564: PCM clock rate when working in assisted modes as a I2S Slave

user4846356
Prodigy 130 points
Part Number: CC2564

Hello

Lets say a CC2564 is connected to a codec via I2S and set to work as an I2S slave and assisted A2DP/HFP. That means the codec should control the BIT clock. 

However since bluetooth audio sample rate varies do to use case, (8 or 16 for HFP 44.1 or 48 for A2DP), the bit clock frequency must also be changed to match the sample rate.

How are these clock changes usually handled? by having the system controller tell the codec to switch clock speed when CC2564 shifts modes?

When CC2564 works as a I2S master, will it automatically change bit clock frequency depending on use case? Is it more reliable to have the CC2564 be set up  as I2S master?

Or does the assisted A2DP/HFP mode contain some sort of sample rate conversion to allow for a constant bit clock?

  • 0
    TI__Mastermind 29301 points

    user4846356 said:
    How are these clock changes usually handled? by having the system controller tell the codec to switch clock speed when CC2564 shifts modes?

    Yes, that is correct. Based on the profile level negotiations, the host MCU/MPU would reconfigure the audio codec IC to change the bit clock speed.

    user4846356 said:
    When CC2564 works as a I2S master, will it automatically change bit clock frequency depending on use case? Is it more reliable to have the CC2564 be set up  as I2S master?

    The profile level negotiations that determine the sample rate to use in a connection are at the profile level (running on top of the host stack). Thus, the CC2564 would not automatically update the sample rate. The host would need to use the HCI_VS_Write_CODEC_Config (0xFD06) to configure the I2S parameters on the CC2564.

    For more details on the system level implementation, please refer to the A3DP sample applications in the following SDKs.

    CC2564CMSP432BTBLESW

    CC2564CSTBTBLESW

    Best regards,

    Vihang