CC2564C: Power-Up Sequencing Inquiry

kevin Lin

Prodigy 185 points

Part Number: CC2564C

hi,

I'm checking the device Power-Up Sequencing for CC2564C in our design.
The measurement result is shown as below:

the fast clock is stable with 22.4 ms of nSHUTD going high,but it require within 20ms in datasheet.

the RTS pulls low with 102 ms of nSHUTD going high,but it require within 100ms in datasheet.

Is this result acceptable for TI's requirement? or any advice to fix it?

Best,

Kevin

over 6 years ago

0 PM over 6 years ago

TI__Mastermind 27145 points

Hi,

As per the data sheet specs, you better to fix it.

Thanks,

0 kevin Lin over 6 years ago in reply to PM

Prodigy 185 points

hi,

Could you give us some suggestions for this issue? Is it because our settling time for XTAL too long?

best,

kevin

0 PM over 6 years ago in reply to kevin Lin

TI__Mastermind 27145 points

Hi,

Did you follow our Reference Design in doing your Schematic and PCB Layout?

Could you please post your Schematic (in PDF) and PCB Layout (in Gerber format) for review?

If you don't want to share your design in the open forum then you can send me a Friend Request then it will open a Private channel.

Thanks,

0 kevin Lin over 6 years ago in reply to PM

Prodigy 185 points

Hi PM,

I already send you a Friend Request. Schematic should be sent in private.

best,

kevin

0 PM over 6 years ago in reply to kevin Lin

TI__Mastermind 27145 points

Hi Kevin,

I accepted your friend request.

Please send Schematic in PDF and PCB Layout in Gerber format for review.

Thanks,

0 PM over 6 years ago in reply to PM

TI__Mastermind 27145 points

Hi Kevin,

I reviewed your Schematic and sent the response through the private channel.

Thanks,

0 kevin Lin over 6 years ago in reply to PM

Prodigy 185 points

Hi PM,

I change the crystal with 8pF load capacitance(a similar model), and the following figures are the test results. I also attached a result of relation between VDD, VDDIO, and sHSUTD in the end.

After the crystal is change, the settling time is decreased around 1 ms, but still fail the specification.

i'm wondering whether the PLL circuit is activated when fast_CLK pin is with a DC. Is there any other reason that make PLL enable slowly?

Best,

Kevin

0 PM over 6 years ago in reply to kevin Lin

TI__Mastermind 27145 points

Hi Kevin,

I don't see any other reason for this issue.

Do you have our Reference Design? If you have it, could you repeat the test on that?

As your measurements are very close (within 10%) to the Spec, you can go ahead with the design. It may not create any issue.

Thanks,

0 kevin Lin over 6 years ago in reply to PM

Prodigy 185 points

Hi PM,

Got it. Thanks for the help!

Best,

Kevin

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CC2564C: Power-Up Sequencing Inquiry