• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 51 subscribers
  • Views 350 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/CC2640R2F: What is the real physical start address of the last page of CACHE?

heng fu
Expert 1020 points
Part Number: CC2640R2F
Other Parts Discussed in Thread: CC2640

Tool/software: Code Composer Studio

1.CONTENT:

       According to the SDK, “If you are using one SNV page(OSAL_SVN=1)you can only use the last 4KB of the GPRAM”, as shown in picture 1 . The link of picture 1 is shown as followed .

http://dev.ti.com/tirex/content/simplelink_cc2640r2_sdk_3_10_00_15/docs/blestack/ble_user_guide/html/ble-stack-common/cache-as-ram.html?highlight=compaction#null

 

Picture 1

 

       My project is based on the simple peripheral project . I have already configured the OSAL_SNV as 1 , and configured the CACHE as RAM .

 

       However ,after configuring the CACHE as RAM , it was find out that the first 4KB of GPRAM was used , as a matter of fact that several .obj objects were moved into the first 4KB of GPRAM automatically . The map file of my project is shown in picture 2 . My complete map file can be downloaded from attachment[1] .  

 

Picture 2

 

       Total size of the CACHE is 8KB . In my mind , according to the CC2640 memory map file , as shown in picture 3 , the start address of the first page of the CACHE is 0X11000000 , and the end address of the first page of the CACHE is 0X 11000FFF. The start address of the last page 0X11001000, the end address of the last page is 0X11001FFF, as shown in picture 3.

Picture 3

 

       According to the SDK, only the last 4KB of the GPRAM can be used in my project . However , the first 4KB of the GPRAM has already been used , which is the result of configuring CACHE as RAM . I cannot believe that the guide of configuring CACHE as RAM in SDK didn’t taking “OSAL_SVN=1” into account . The link of the guide is shown as followed :

http://dev.ti.com/tirex/content/simplelink_cc2640r2_sdk_3_10_00_15/docs/blestack/ble_user_guide/html/ble-stack-common/cache-as-ram.html?highlight=compaction#section-cache-as-ram-configure-cache

 

. So I am really confused about the real physical start address of the last page of CACHE . What is the real physical start address of the last page of CACHE? Where am I wrong ?

 

 

 

2.Attachments:

[1]the positon of simple_peripheral project in my computer is as followed:

E:\ti\simplelink_cc2640r2_sdk_3_10_00_15\examples\rtos\CC2640R2_LAUNCHXL\blestack\simple_peripheral

 

[2]the complete map file of my project can be downloaded here :

cc2640.rar

 

3.my develop invironment:

CCS: Code Composer Studio 9.1.0

SDK: simplelink_cc2640r2_sdk_3_10_00_15

hardware:CC26640R2 develop kit

  • 0
    TI__Guru 56335 points

    Hi,

    In the software user's guide, it says specifically that even when you enable CACHE_AS_RAM with osal_snv = 1, the cache will be used as GPRAM to store data.

    The data will be saved from the start till the end of GPRAM. However, if a compaction is needed, the first half of GPRAM will be overriden and result in data corruption.

    What you need to do is to make sure osal_snv = 2, so that when compaction is needed, it will use flash to do the compaction instead of first page of GPRAM.