CC2642R: CC2642 power on reset sequence

Hiroki Hatsuda

Part Number: CC2642R

Hi.

CC2642 has power on reset.

Could you tell me the power on reset sequence and ansewer the following questions.

1. Is there any restriction on the timing of VDD ON to reset release?
2. 48MHz oscillation stabilization wait time inside the CC2642 when VDD is ON.
3. Time from VDD ON to software start.

4. When VDD OFF → VDD ON, there are restrictions on time and voltage required for generating power-on clear.

BR Hiroki

CC2642 power on reset sequence.xlsx

over 5 years ago

0 TER over 5 years ago

TI__Guru**** 317180 points

What is the background for these questions?

1) No. I would ensure that VDDS is above 1.8 V before releasing the reset pin to ensure that you don't get a POR when you release the reset pin.

2) Note that the 48 MHz xtal only starts up when using RF. The 48 MHz RC OSC starts up after power on.

3) I will generate a plot that shows the timing.

4) Not that I'm aware of.

0 Hiroki Hatsuda over 5 years ago in reply to TER

Intellectual 430 points

Hello.

Thank you for your reply.

I am waiting for the timing chart of power-on reset.

BR Hiroki

0 Vegard H over 5 years ago in reply to Hiroki Hatsuda

TI__Expert 4560 points

Hi Hikori

The startup sequence usually takes around 13 ms, which is this point after the power up.

Regards,
Vegard

0 Vegard H over 5 years ago in reply to Vegard H

TI__Expert 4560 points

Hi

Here is a better timing chart when powering the device.

The program time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again.

The timing from when the VDDS crosses the threshold to when the POR is released is in the ns range, since this is only controlled by a comparator.

Regards,
Vegard

0 Hiroki Hatsuda over 5 years ago in reply to Vegard H

Intellectual 430 points

Hi.

Thank you for your reply.

One more question.

What is the voltage range of VDDS which keep low level of POR signal?

BR Hiroki

0 Vegard H over 5 years ago in reply to Hiroki Hatsuda

TI__Expert 4560 points

Hi Hiroki

In the datasheet, section 5.4 gives information on the values before POR/BOD is released.

This can be visualized the following way.

Regards,
Vegard

0 Isao Takigasaki over 5 years ago in reply to Vegard H

TI__Expert 3350 points

Hi, Vegard

I believe user4488101 want to know the device behavior related to POR/BOD in all power sequence which can be assumed to verify their system with this device.

Could you fill the diagram in below?

0 Vegard H over 5 years ago in reply to Isao Takigasaki

TI__Expert 4560 points

Here is a diagram of the different cases:

0 Isao Takigasaki over 5 years ago in reply to Vegard H

TI__Expert 3350 points

It helps to understand the power-up sequence. Thank you.

Please let me also confirm the enough voltage dip to reset the device. In the following figure, I think the device can be reset in the case dip #2 with deep valley and long period. Could you provide enough voltage dip voltage and period?

I think parasitic capacitance of each nodes in the device have to be discharged or any bigger capacitance in the device have to be discharged to restart correctly.

0 Vegard H over 5 years ago in reply to Isao Takigasaki

TI__Expert 4560 points

Hi.

Correct, the voltage dip required depends on the manufacturing of the device. The POR uses a comparator with resistors to check if the voltage is above a certain treshold. Depending on the cornering of the device, this resistance can vary a lot.

Regards,
Vegard

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CC2642R: CC2642 power on reset sequence