Other Parts Discussed in Thread: CC2640
Hi team,
According the datasheet ,the fistly flash erase time is 8ms,but give the trends of erasing many times. So Would you give us about it or give the largest time.
We account it in our project.as follow.
The test analysis of question 1 is as follows:
1. The backdoor and reset timing and waveform of control and communication between the main chip and cc2640 are normal, and the SPI waveform is normal.
2. The software normally enters backdoor when upgrading through the serial port. After sending the erase command, it does not receive the ack of cc2640. The software accepts the ACK timeout and the upgrade fails.
3. The upgrade is successful by increasing the ACK wait time.
In conclusion, it is suspected that flash will increase with the number of erasures. The software received ack timeout and upgrade failed.
The test analysis of question 2 is as follows:
1. By increasing the ACK wait time, the upgrade still fails.
2. The smart RF flash prgrammer2 on the TI official website is used to forcibly erase the chip in question. Reading the flash, it is found that there is an error starting from page 23 (address 0x00017000), some of which are not FF; and it is the same for many times of forcible erasure. The read bin is as attachment.
To sum up, it is suspected that the bad block appears after multiple erasions, resulting in the forced erasure failure.
Thanks
