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CC2652P: What's the maximum SPI CLK frequency supported by CC2652P in master mode?

Part Number: CC2652P

Hi there, I use CC2652P.

In this user manual, 

description on SPI clock is this:

PERDMACLK is 48MHz, according to register description, CPSDVSR minimum is 2, SCR minimum is 0, so the maximum clock is 48MHz/[2*(1+0)]=24MHz. (SPI is master mode)

However, according to datasheet, the minimum clk cycle S1 is 12 system clocks. System clock is 48MHz, so maximum spi clock is 48MHz/12 = 4MHz.

And in another chapter in datasheet, an explicit description tells that the maximum spi clock is 4MHz too.

But, in SDK v4.20, another different description again, 12MHz (master mode).

So SPI clock maximum frequency in master mode is : 

(1), In Technical Reference Manual, 24MHz;

(2), In datasheet, 4MHz;

(3), In SDK, 12MHz.

I'm confused about this.

What's the real maximum SPI CLK frequency supported by CC2652P in master mode?

  • Hi Yingtao,

    I understand this could be confusing, I would break it down like this:

    1) Gives you the theoretical maximum speed of the hardware in question. In other words, it could for example do at most 24 MHz as a master.

    2) The data sheets notes that the numbers are in relation to the TI-Drivers. As such, they note the highest common for both slave and master, which is 4 MHz. Only master could go higher.

    3) This is the driver verified numbers, 4 MHz for slave (which is the number quoted in the datasheet as it is the highest common for both slave and master) and 12 MHz for master. 

    While the HW theoretically could go higher, the limits given in the driver is the "safe" maximum for which full duplex is verified in lab. Doing full duplex at higher clock rates may or may not work as intended (meaning you might be getting data corruption on the RX side). I have seen customers running full 24 MHz master one way communications without an issue.

    The driver will not stop you from running at a higher clock rate if you want to try it.