CC2564C: IO rise/fall time and PCM clock accuracy

I try to use VS_Set_Pcm_Loopback to loop PCM and check cc2564c data out

(WS, BT Dout, BT Din)

(we change level shifter circuit for reduce Tr, Tf )

Data in and data out is same. 

thanks

Update,

according to "CC256xB BT Service Pack CC256XB_BT_SP_v1.8 Release Notes", tick and device lockup problem in slave mode fixed ! . I can't find recommended PCM clock range for CC256XB or CC2564C in datasheet or "CC2564C BT Service Pack CC256XC_BT_SP_v1.4 Release Notes"

.

thanks

Hi Vincent,

thanks for your replay

what's the means of " exactly set for the correct bit rate" ? cc2564c need to "0 ppm" accuracy?

according to android bt_snoop log, in HFP our MCU is master and smart phone is slave and I think little variation must be acceptable 

our design is mass product development and many parameter can cause little variation in PCM clock

we test design as hard as possible but can you please introduce official document for PCM valid accuracy in ppm?

thanks 

Vincent,

thanks for recommendation

Ok we try to meet 100 ppm.

and about first question, because of design constraint, our rise/fall time for UART and PCM is ~20ns instead of datasheet recommend values (10ns and 2.5ns)

PCM loop back test is OK and for UART HCI 3-wire (H5), we haven't "retransmit warning" on cc256x logger. 

Is recommended Tr, Tf of PCM and UART necessary for correct function?

what problems can occur due to our Tr and Tr values?

thanks for your time

Vincent,

thanks for your reply

best regard