Assuming the system-clock is 48MHz (external 24MHz clock signal), I have some questions on the rising-edge detection for the CC26x0 devices.
From the Technical Reference Manual:
For rising-edge detection, the input signal must be high for at least two system-clock periods following the rising edge. Similarly, for falling-edge detection, the input signal must be low for at least two system-clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is ¼ of the system frequency.
[1] Is there any timing diagram showing an example of this, with the system-clock and the timing from an edge happening, to the count register getting updated?
[2] If falling-edge detection is not a care-about, how much time after the input signal falling edge is needed to detect the next rising edge? Does this ¼ of the system frequency limit still apply?
P310 of the attached Renesas MCU user manual gives such an example. RL78/G13 User's Manual: Hardware
In this example, they show the "system-clock" as f_mck.
After a rising edge on the external timer input, the f_mck has a rising edge ->
on the next rising edge, it triggers the "edge detected" signal (= count clock),
and then on the falling edge of that 2nd f_clk pulse, the value in the count register changes.
From the above, it looks like Renesas is using one system-clock period (two system clock rising edges) to detect a rising-edge event.
Because of this, it looks like assuming a 32MHz system-clock (f_mck), they can detect up to 1/2 the f_mck, or in this case, up to 16MHz.
But our solution needs two system-clock periods to detect an edge, so we can only do up to 12MHz, right?
Darren
