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CC2564C: Small audio dropouts occuring repeatedly

awu@seantec

Intellectual 270 points

Part Number: CC2564C
Other Parts Discussed in Thread: TLV320AIC3254, CC2564

I have the BTchip working with A3DP profile. Music is playing but from time to time there are short audio drops. Looking at the logic analyzer revealed that the bitclock shows some weird behavior: due to repeated Fsync signal (4.68 us instead of 22.32 us) the bitclock signal remains active but the AudioOut-signal shows no activity. This breaks the normal operation cycle and later one bitclock sample is missing, completely. However, there is some AudioOut-signal visible while bitclock is inactive low.

After that the firmware running on MSP432 does synchronize on the fsync signal and audio becomes hearable as before this weird dropout. This happens in random intervalls.

What can be the cause of this?

Remark: I configured the Bluetopia stack to keep the bitclock running only during the sample period and then shutdown bitclock until next fsync pulse. This way I'm able to capture the digital audio from BTmod via SPI with MSP432P401A for further processing.

over 5 years ago

0 Hari Nagalla over 5 years ago

TI__Mastermind 27470 points

What is the sample rate being used? Is it 44.1K or 48K? Can, you also take the FW logs?

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

The sample rate is 44.1 kHz.

What exactly do you mean by FW logs? Please find attached the initialization log from the firmware.

The firmware running at MSP432P401R is based on A3DPDemo_SNK from Bluetopia SDK. The major difference is that digital audio interface from CC2564C is connected to one SPI-port and digital audio interface of Codec is connected to a different SPI-port. The captured audio data are being transferred to a memory buffer (one for each SPI) via DMA. The memory buffers have a size of 16 bytes each so it can hold exactly 8 audio samples of 16 bits.

Furthermore, I added HFP support to the firmware similar to as described in this guide from TI. But since I'm starting the firmware in A3DP this shouldn't affect the use case. Switching from A3DP to HFP is a completely different story...

Fullscreen startup.log Download

OpenStack().
Bluetooth Stack ID: 1
Port Number: 1
HFRE_Open_HandsFree_Server_Port: Function Successful.
HFRE_Register_HandsFree_SDP_Record: Function Successful.
WBS Support initialized.
Device Chipset: 4.2
BTPS Version  : 4.2.1.0
Project Type  : 6
FW Version    : 12.23
App Name      : aPitiBlu
App Version   : 0.1
BD_ADDR: 0x3415137FF91E
A3DP endpoint opened successfully.
Class of Device: 0x090460.
Supported formats:
   Frequency: 44100, Channels: 2, Flags: 0
   Frequency: 48000, Channels: 2, Flags: 0
   Frequency: 48000, Channels: 1, Flags: 0
   Frequency: 44100, Channels: 1, Flags: 0

******************************************************************
* Command Options: Inquiry, DisplayInquiryList, Pair,            *
*                  EndPairing, PINCodeResponse, PassKeyResponse, *
*                  UserConfirmationResponse,                     *
*                  SetDiscoverabilityMode, SetConnectabilityMode,*
*                  SetPairabilityMode, SetBaudRate               *
*                  ChangeSimplePairingParameters,                *
*                  GetLocalAddress, GetLocalName, SetLocalName,  *
*                  GetClassOfDevice, SetClassOfDevice,           *
*                  GetRemoteName, OpenSink, CloseSink,           *
*                  RemotePlay, RemotePause, RemoteNext,          *
*                  RemotePrev, Help                              *
******************************************************************


A3DP+SNK>

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

I mean controller FW logs.

3554.CC256x Logger User Guide - Texas Instruments Wiki.pdf

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

I would love to attach the log for pairing, start of playing and after the drop occurred I stopped playing. However, after upload the form becomes empty and I cannot attach anything. I tried attaching the original .lgr-file and the same encapsulated in a 7zip - both without success.

But after I added dropout detection to my firmware I can match exactly what happens in the controller FW logs when the dropout occurs:

3131	21:31:47.899   +0:00:21.835	LC Inquiry Scan - Start, LAP=0x9e8b33, Window=9 frames	
3132	21:31:47.899   +0:00:21.835	synch cmd return event STARTED,module INQUIRY SCAN	
3133	21:31:47.899   +0:00:21.835	synch event FINISH received, module INQUIRY SCAN, msi 1	
3134	21:31:47.899   +0:00:21.835	synch cmd start instance, module ACTIVE CONNECTION, msi: 10	
3135	21:31:47.899   +0:00:21.835	synch cmd return event STARTED,module ACTIVE CONNECTION	
3136	21:31:48.273   +0:00:22.209	HCILL send command: HCILL_WAKE_UP_IND_MSG	
3137	21:31:48.273   +0:00:22.209	HCILL state machine is: WAITING FOR WAKE UP ACK	
3138	21:31:48.273   +0:00:22.209	HCILL received command: HCILL_WAKE_UP_ACK_MSG	
3139	21:31:48.273   +0:00:22.209	HCILL release_transmit_queue	
3140	21:31:48.273   +0:00:22.209	HCILL state machine is: AWAKE	
3141	21:31:48.363   +0:00:22.299	HCILL send command: HCILL_GOTO_SLEEP_IND_MSG	
3142	21:31:48.363   +0:00:22.299	HCILL state machine is: WAITING FOR SLEEP ACK	
3143	21:31:48.363   +0:00:22.299	HCILL received command: HCILL_GOTO_SLEEP_ACK_MSG	
3144	21:31:48.363   +0:00:22.299	HCILL state machine is: SLEEP	
3145	21:31:48.408   +0:00:22.344	ACL_DATA_STATISTICS for LC handle 0: Rx bps - 335745 , Tx bps - 14 , remote NACK ratio - 0

The dropout has been printed out in serial terminal connected to a different COM-port with timestamp-logging enabled. And here it is with timestamp:

[2021-04-19 21:31:48.252] A3DP+SNK>
[2021-04-19 21:31:48.253] A3DP+SNK>Drop!
[2021-04-19 21:31:51.871] Drop!

Later on, right before stopping the playback, there was another drop being reported by my firmware. First the content from HCI-logger:

7258	21:32:11.544   +0:00:45.480	HCILL send command: HCILL_WAKE_UP_IND_MSG	
7259	21:32:11.544   +0:00:45.480	HCILL state machine is: WAITING FOR WAKE UP ACK	
7260	21:32:11.544   +0:00:45.480	HCILL received command: HCILL_WAKE_UP_ACK_MSG	
7261	21:32:11.544   +0:00:45.480	HCILL release_transmit_queue	
7262	21:32:11.544   +0:00:45.480	HCILL state machine is: AWAKE	
7263	21:32:11.635   +0:00:45.571	HCILL send command: HCILL_GOTO_SLEEP_IND_MSG	
7264	21:32:11.635   +0:00:45.571	HCILL state machine is: WAITING FOR SLEEP ACK	
7265	21:32:11.635   +0:00:45.571	HCILL received command: HCILL_GOTO_SLEEP_ACK_MSG	
7266	21:32:11.635   +0:00:45.571	HCILL state machine is: SLEEP	
7267	21:32:12.010   +0:00:45.946	0x0000BE26	0x0000BE26	HCI_VS_A3DP_Sink_Stop_Stream	---->	
7268	21:32:12.010   +0:00:45.946	0x0000BE27	0x0000BE27	<----	HCI_Command_Complete_VS_A3DP_Sink_Stop_Stream_Event	
7269	21:32:12.011   +0:00:45.947	A3DP SINK: UNDERRUN 1	
7270	21:32:12.011   +0:00:45.947	AVPR received a message from ARM [0x0017], number 23	
7271	21:32:12.011   +0:00:45.947	HCILL send command: HCILL_WAKE_UP_IND_MSG	
7272	21:32:12.011   +0:00:45.947	HCILL state machine is: WAITING FOR WAKE UP ACK	
7273	21:32:12.011   +0:00:45.947	HCILL received command: HCILL_WAKE_UP_ACK_MSG	
7274	21:32:12.011   +0:00:45.947	HCILL release_transmit_queue	
7275	21:32:12.011   +0:00:45.947	HCILL state machine is: AWAKE	
7276	21:32:12.011   +0:00:45.947	hcic_process_hci_commands: HCIPP_A3DP_SNK_STOP_STREAM (Group 3f Opcode 0x19e)	
7277	21:32:12.011   +0:00:45.947	hcic_get_num_of_host_commands. Total free = 3, Reported to host = 1	
7278	21:32:12.011   +0:00:45.947	HCI Send Event: HCI_COMMAND_COMPLETE_EVT	
7279	21:32:12.011   +0:00:45.947	AVPR received a message from ARM A3DP_SNK_STOP_STREAM_COMMAND, number 21	
7280	21:32:12.011   +0:00:45.947	A3DP SINK: stop stream flush_flag 1

And here is the timestamp from dropout message:

[2021-04-19 21:32:11.524] A3DP+SNK>Drop!

Really hope you can make some sense out of this.

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

You should be able to upload the *.lgr files. Otherwise, please rename it to .txt and send it across..

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

A3DP-playing9a.lgr.txt

Okay, the trick with renaming seems to work. One remark to the dropout detection in firmware: due to its nature this has some delay compared to what you see in the FW-log. But the maximum possible delay is 1.5 ms (i.e. 64 audio samples at 44.1 kHz) so it should be negligable. And here are the timestamps from the dropouts occurred during the logging above:

[2021-04-20 21:21:41.788] Drop!
[2021-04-20 21:21:55.142] Drop!
[2021-04-20 21:21:55.194] Drop!
[2021-04-20 21:22:08.511] Drop!

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

Can, you provide details of how the codec is connected? Is it expecting a I2s interface i.e 50% duty cycle. It appears, you may need to correct the PCM/Codec configuration on the CC2564C controller i.e HCI_VS_Write_Codec_Config.5584.CC256x VS HCI Commands - Texas Instruments Wiki.pdf

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

Here we go: this is the function which configures the audio codec of BTmod:
<edit>The value of HRDWCFG_SPI_DIVIDER is 8 and the SMCLK is providing 24 MHz</edit>

static void ConfigureControllerAudioCodec(unsigned int BluetoothStackID, unsigned long SamplingFrequency, unsigned int NumChannels)
{
   Word_t Channel1Offset;
   Word_t Channel2Offset;

   union
   {
      VS_Write_Codec_Config_Params_t          WriteCodecConfigParams;
      VS_Write_Codec_Config_Enhanced_Params_t WriteCodecConfigEnhancedParams;
   } u;

   Channel1Offset = 0;
   Channel2Offset = Channel1Offset + 16;
   BTPS_MemInitialize(&u.WriteCodecConfigParams, 0, sizeof(u.WriteCodecConfigParams));
   // Adjust PCMclock to a value which can be used for SPI transfers:
   u.WriteCodecConfigParams.PCMClockRate_KHz      = CS_getSMCLK() / HRDWCFG_SPI_DIVIDER / 1000;
   u.WriteCodecConfigParams.FrameSyncFrequency_Hz = (DWord_t)SamplingFrequency;
   u.WriteCodecConfigParams.FrameSyncDutyCycle    = 0x0001;
   u.WriteCodecConfigParams.CH1DataOutSize        = 16;
   u.WriteCodecConfigParams.CH1DataOutOffset      = Channel1Offset;
   u.WriteCodecConfigParams.CH1DataInSize         = 16;
   u.WriteCodecConfigParams.CH1DataInOffset       = Channel1Offset;
   u.WriteCodecConfigParams.CH1InEdge             = 1;
   u.WriteCodecConfigParams.CH2DataOutSize        = 16;
   u.WriteCodecConfigParams.CH2DataOutOffset      = Channel2Offset;
   u.WriteCodecConfigParams.CH2DataInSize         = 16;
   u.WriteCodecConfigParams.CH2DataInOffset       = Channel2Offset;
   u.WriteCodecConfigParams.CH2InEdge             = 1;
   VS_Write_Codec_Config(BluetoothStackID, &u.WriteCodecConfigParams);

   /* Set the codec config enhanced parameters.                         */
   BTPS_MemInitialize(&u.WriteCodecConfigEnhancedParams, 0, sizeof(u.WriteCodecConfigEnhancedParams));
   u.WriteCodecConfigEnhancedParams.PCMClockShutdown = 0x01;
   u.WriteCodecConfigEnhancedParams.PCMClockStart  = 0x0000;
   u.WriteCodecConfigEnhancedParams.PCMClockStop   = 0x001F;    // Disable clock after 32 clock cycles
   u.WriteCodecConfigEnhancedParams.CH1DataOutMode = 0x01;
   u.WriteCodecConfigEnhancedParams.CH2DataOutMode = 0x01;
   VS_Write_Codec_Config_Enhanced(BluetoothStackID, &u.WriteCodecConfigEnhancedParams);
}

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

Did, you take the above codec config from some where Or did you do it yourself? Which codec is being? Is it TLV320AIC3254? Did, you try the codec configuration, as provided in the MSP432 BluetopiaSDK, A3DPDemo_SNK example?

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

I started with the codec config from A3DPDemo_SNK example and did adjust it to my needs the following way:

Make Channel1Offset = 0 to start sampling on the first edge of bitclock.
Adjust the PCMClockRate_kHz to a value which can be used for SPI bitclock as well.
Add PCMClockShutdown, PCMClockStart, PCMClockStop to the enhanced parameters to enable MSP432 capturing/transmitting audio data through SPI module.

(I think) this configures the codec from BTmod CC2564C which very likely is TLV320AIC3254, as you mentioned, because I have been pointed to its manual in a different thread.

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

We are currently busy with other things. Will, get back in couple of days..

Thanks

0 Hari Nagalla over 5 years ago in reply to Hari Nagalla

TI__Mastermind 27470 points

It is not clear why SPI bit clock is coming into picture. It seems, you are configuring the PCM clock for 3MHz and the sample frequency at 44.1K Hz. The PCM clock is not an integer multiple of sampling frequency, so you may have issues. Try to make PCM clock an integer multiple of sampling frequency. Else, configure 'FSyncMultiplier' to 32 or 64. This makes the controller adjust the PCM clock.

Also, let the PCM clock be active all the time.

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

You described the situation quite precisely: the PCM-clock is configured for 3 MHz enabling me to capture the audio samples using the SPI module of MSP432P401R running at the exact same bitclock speed. I didn't found any SPI-clock supported by MSP432P401R which matches a multiple of sampling frequency of 44.1 kHz.

And due to the nature of SPI I cannot manage to keep the PCM clock active all the time - this way I would have to somehow throw away the dummy samples (hope the name makes sense) read by SPI module after the left and right channel have been transmitted.

Where/how should I configure FSyncMultiplier and what does this actually mean?

I'm afraid I begin to understand: the PCM-clock appearantly /has/ /to/ /be/ an integer multiple of sampling frequency, right?

Is there any chance to capture the audio from BTmod using MSP432P401R? I mean my current configuration is working despite the (somehow) periodic audio drops or (like I would call it now) synchronization issues.

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

I am not familiar with your setup and the need of SPI. Any ways, attached if the CC2564x VS commands. I do not think you can capture the audio on MSP432.

3718.CC256x VS HCI Commands - Texas Instruments Wiki.pdf

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

Short update: I am already able to capture the audio; it is working for a few seconds until the misbehavior of CC2564C described above occurs. Furthermore, I managed in MSP432P401R firmware to sync again on framesync signal supplied by CC2564C. Alas, this process is /hearable/ to the user and nobody will accept this in the final product.

Hari Nagalla, I'm going to show you a component diagram of my setup here in this thread. If you are interested I can also send you the circiut diagram by PM.

0 awu@seantec over 5 years ago in reply to awu@seantec

Intellectual 270 points

Here is the (reduced) component diagram - please remove the txt-extension to view as SVG.

Fullscreen CompDiagram.svg.txt Download

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0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

Can, you send pdf version of the diagram?

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

Yes, I can:

CompDiagram.pdf

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

I see the diagram now.. Why can't the CC2564C directly gets connected to the MAxim9867 codec? What sort of signal processing is done on MSP432?

I suggest try with the Default configuration provided in the Demo first..

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

Thank you for sharing your idea.

In our setup there is only one audio codec that we use for record + playback. However, we intend to use different sources for playback. One is the BT-module and another is e.g. external memory of the µC. Since we cannot connect these different sources to that single codec, we connect the MSP to the Max9867 only. Therefore we need to make it work.

Furthermore, the issue arises outside MSP432 - as shown in logic analyzer above. In an early development phase we tested the direct connection between CC2564C and Max9867, successfully. However, in that case the codec inside CC2564C is configured in a different way - matching the specifications you mentioned above (PCM clock being a multiple of sampling frequency and PCM clock being active all the time).

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

I see.. Let me get back in couple of days..

Thanks

0 Hari Nagalla over 5 years ago in reply to Hari Nagalla

TI__Mastermind 27470 points

IMO, when you are routing PCM like this you would need rate adaptations on the MSP432, because on one side it is acting as a PCM slave and on the other as a PCM master. Did, you consider using CC2564C as the master the same PCM bus wired to both MSP432 and Max9867 codec? ofcourse the 'Audio out' from CC2564C and MSP432 need a switch to select one to the MAx 9867 codec.

In this scenario, you can keep the PCM bit clock and FSYNC active all the time from CC2564C.

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

Thank you for getting back to this topic.

The setup you are describing as an alternative solution is similar to what we had for our proof of concept hardware: there already was a switch to shortcut the 'Audio out' from BTmod to 'Audio in' on the Max9867 codec (and Fsync, bitclock as well) and it was working exactly the way you described without further interaction from MSP432. However, this was the A-sample hardware and for the final product there even must /not/ be such a connection possible.

What is the meaning behind "rate adaptations" on the MSP432 and how can I achieve these? Yes, towards CC2564C the controller is PCM slave and for the Max9867 codec the controller is PCM master. Is it possible to make the CC2564C act as PCM slave as well - and could this possibly resolve the issue?

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

I meant, there may be different PCM clock drifts when interfaced on two PCM Buses. This could lead to underrun or overflow of samples over time. With Rate adaptation, i meant to compensate for these drifts across the PCM I/Fs. Is the PCM bit clock rate the same with CC2564C and the Max9867 codec?

You can also try configuring CC2564C as slave.

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

I already identified the drift as an issue. And here is what I did to resolve this:

Synchronise capturing on frame sync signal from CC2564C via interrupt from P2.4.
Start SPI with DMA to send 16 bytes (i.e. 4 samples left and 4 samples right channel) towards Max9867, triggered by Timer_A3 with appropriate period to match sampling frequency.
Furthermore, Timer_A3_CCR2 will trigger P8.2 to serve the LRCLK signal of Max9867.
Start to capture audio samples from CC2564C using EUSCI_B2, continuously. Capturing is done by DMA: copy 16 bytes and then DMA complete interrupt occurs.
Important: disable the framesync interrupt.
After DMA has completed:
Enable framesync interrupt
Restart DMA channel to continue capturing on next frame sync edge (step 3).
Upon framesync interrupt:
Explicitely set the counter value of Timer_A3 controlling DMA transfer towards Max9867 on a certain value (examined by breakpoint hit at this time). This way any possible drift between Fsync towards Maxim and Fsync from CC2564C is eliminated.

The starting point of Timer_A3 has been choosen in a way it never expires during framesync interrupt. Furthermore, by checking how many bytes have been transferred (by DMA) towards Max9867 at this point I can detect the situation described in the first post of this thread and restart the synchronisation procedure from the beginning.

I couldn't find out how to run the CC2564C audio interface as slave - how do I achieve/configure this?

0 awu@seantec over 5 years ago in reply to awu@seantec

Intellectual 270 points

Forgot to mention an important point: the first DMA transfer towards Max9867 is only half the size - this way every next transfer should be /exactly/ half-way finished when framesync signal from CC2564 arrives. If it isn't something went wrong and we need to resync, again.

0 Hari Nagalla over 5 years ago in reply to awu@seantec

TI__Mastermind 27470 points

I am not an expert on MSP432 DMA architectures, so please check with that forum. As mentioned earlier, you may also try with MSP432 as the PCM master for both PCM buses. Please refer to the A3DP Demo_snk sample from CC2564CBT stack for STM32. In this example STM32F4 MCU is the PCM master.

https://www.ti.com/tool/CC2564CSTBTBLESW

Thanks

0 Hari Nagalla over 5 years ago in reply to Hari Nagalla

TI__Mastermind 27470 points

Have you tried with MSP432 being the PCM master for both connections? If there are issues please raise a new query. I will close this.

Thanks

0 awu@seantec over 5 years ago in reply to Hari Nagalla

Intellectual 270 points

Hari Nagalla, thank you very much again for looking into this and providing your ideas!

Finally, I made it to run the CC2564C digital audio interface as slave (because I could swap the SIMO/SOMI pins using the portmapper in MSP432 - great feature). I even was able to switch from Fsync pulse to LRCLK signal and the audio became hearable, eventually.

Alas, the short glitches are still the same! Only the appearance in logic analyzer is different. They occur in irregular intervals. I'm going to follow your advice and raise a new query.