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TRF7964A: 15693协议,标签芯片已经返回数据,但是FIFO里面没有数据

Part Number: TRF7964A

15693协议,使用260100指令,请求读取标签UID,标签已经返回数据(可以再OOK/ASK引脚看到信号),但是TRF7964A的FIFO里面没有数据

IRQ Status Register (0x0C),这个中断寄存器里面已经收到0x40标志(IRQ set due to RX start),并且等到IRQ引脚有效,再次去读取FIFO长度寄存器,显示FIFO长度数据是0

这个情况不是每次都能出现,但是一旦出现后,通过软件复位TRF7964A,没有效果,情况依然存在

IRQ Status Register (0x0C)中断寄存器中 

CRC error

Parity error

Byte framing or EOF error

Collision error

No response time interrupt

这些标志位都是0

  • Hi Wenwu,

    can you please repeat your question in English.

    Best Regards,

    Helfried

  • trf7964A work in iso15693, when the ic tx cmd(260100), the tag response the cmd , and i can see the subcarrier signal at pin12, but the fifo len is zero in fifo status reg, the irq status reg don't have the error flags. 

  • Hi Wenwu,

    are you resetting the FIFO after receiving the TX interrupt as described in the FAQ chapter 4.6:

    https://www.ti.com/lit/pdf/sloa248

    What is the command you are sending? It is not clear for me what ISO command 260100 is.

    Best Regards,

    Helfried

  • hi !

    this is my c code.

    while(tick < waitTime)   //wait timeout
        {
            if(Trf796x_GetIrqState())   //get the irq pin status
            {
                flag = Trf796x_ReadReg(TRF796X_REG_IRQ_STATUS);  //read irq reg
                if(flag & TRF796X_REG_ERR_MSK)                     //if the reg value is error code, stop receive the tag rsp.
                {
                    err = Trf796x_FmtErrInfo(flag & TRF796X_REG_ERR_MSK);
                    break;
                }
                else if(flag & TRF796X_REG_IRQ_TX_END)             //if the reg value is tx end, cleat the fifo
                {
                    Trf796x_WriteCmd(TRF796X_CMD_RESET_FIFO);   //清空FIFO
                }
                else if(flag & TRF796X_REG_IRQ_FIFO_LV)          //
                {
                    err = Trf796x_FmtErrInfo(flag & TRF796X_REG_ERR_MSK);
                }
                else
                {
                    if(flag & TRF796X_REG_IRQ_RX_START) //if the reg value, read the tag rsp.
                    {
                        err = TRF796X_ERR_OK;
                        err = Trf796x_ReadReg(TRF796X_REG_IRQ_STATUS);
                        rxFifoLen = Trf796x_ReadReg(TRF796X_REG_FIFO_CONTROL) & TRF796X_REG_FIFO_RXLEN_MSK;
                        Trf796x_ReadRegs(TRF796X_REG_FIFO, rxFifoLen, pTrf76xFrame->frame + pTrf76xFrame->rxLen);
                        pTrf76xFrame->rxLen = rxFifoLen;
                        break;
                    }
                }
            }
            tick++;
        }

    the bug is: the tag in the ant, the tag respons the cmd(260100---15693 inventory one tag),   trf7964a can read the RX_START flag, but the fifo length is zero.

    the bug doesn't appear every time.

  • Hi,

    as far as I can see the code looks good. The only thing that makes we wonder is that the code runs in a loop and is not setup as an interrupt service routine. Because resetting the FIFO should be done immediate after the TX ready IRQ this is maybe not fast enough in your case.

    Best Regards,

    Helfried 

  • The spi speed is 9Mhz, it is very fast.

    The cpu speed is 72Mhz.

    I think the loop is fast enough, and when cpu receive the tx end flag, the trf7964 must wait 330us receive the tag response sof signal.

    when the fifo length is zero, the subcarrier signal at pin12 is very good.But, why the trf7964 don,t have tag rsp in the fifo?

    sometime, the trf7964 work very good, it can receive the correct tag rsp, and other time ,the trf7964 is not so good .

    why?

  • the trf7964 regs:

    addr------------value

    00----------------20

    01----------------02

    02----------------00

    03----------------00

    04----------------c1

    05----------------bb

    06----------------00

    07----------------14

    08----------------18

    09----------------09

    0a----------------4c

    0b----------------06

    0c----------------00

    0d----------------1f

    0e----------------00

    0f----------------40

    10----------------10

    .----------------00

    .----------------00

    .----------------00

  • Hi,

    You are working with a very fast SPI clock and fast CPU speed. I have checked in the forum if I could find a similar problem and came across a post where the customer needed to insert a delay between detecting the RX start IRQ and checking the FIFO. This was necessary because the RX IRQ signaling the SOF was received not that RX is finished. Maybe this makes a difference.

    Best Regards,

    Helfried

  • Hi,

    I haven’t heard back from you for a while, so this tread is being closed. If you wish to continue the discussion, please post a reply with an update below (or create a new thread).

    Best Regards,
    Helfried