CC2340R5: SPI Timing Diagrams - Controller Mode

Datasheet Reference

• Refer to the CC2340R5 datasheet, Section 6.6 "Electrical Characteristics" or the SPI subsection under "Timing Requirements - Controller Mode." Look for:
  • tSU,CI: Data setup time before SCLK (e.g., 3 ns typical at 48 MHz).
  • tHD,CI: Data hold time after SCLK (e.g., 0 ns min, 2 ns typ).
• These values scale with frequency; at lower clock rates (e.g., 1 MHz), setup/hold times increase proportionally (e.g., 10–20 ns).

Practical Considerations

• Verification: Use an oscilloscope to measure tSU,CI and tHD,CI on your board with the CC2340R53E0YBGR, ensuring POCI aligns with SCLK edges per Figure 7-1. Adjust clock frequency if timing margins are tight.
• Layout: Keep SPI traces short (<10 cm) and matched to minimize skew, as the diagram’s tCS,LEAD, tCS,LAG, and tVALID,CO also impact overall timing.
• Mode: Since SPH = 0, data is clocked on the rising edge, so ensure your peripheral (e.g., sensor) meets these setup/hold requirements. 

Masa, 

Please apologize for the delay. I confirmed with the design team that these timings are fully compliant with the setup and hold timings of the SPI protocol. 

In other words, the setup and hold times are half clock cycle or ~41ns (our maximum clock frequency is 12 MHz). 

Hope this helps,

Rafael