We have been trying the TRF7070A in 14443A card emulation mode, and have a couple of questions about the FIFO Status (0x1C) register:
-- When using the automatic SDD procedure, when the SDD complete interrupt happens, the FIFO Status register is 0x01, indicating 2 bytes are available. What do these bytes represent?
-- The next interrupt following the SDD complete is an RX Complete interrupt. Again 2 bytes are available (FIFO Status = 0x01) which are always 0x50 and 0x70. This seems like it may be related to the HLTA command (0x50 0x00) but the 0x70 is not what was transmitted. What frame responses are included in the automatic SDD handling?
-- The next time we get a SDD Complete interrupt the FIFO Status = 0x7f. It then appears that we have to read 7F bytes to make the FIFO empty (FIFO Status = 0xFF). In the documentation (page 74) bits B4-B6 are documented as being status indication bits. But these appear to be counter bits, and decrement appropriately when the FIFO is read. It also appears that the example code in the Android/BlueTooth example masks the FIFO Status register with 0x7F to get a count. Can we get some clarification on what the meaning of the FIFO status register bits are? Are there different modes?
Thanks,
-dts