TRF7963A: Timing Conditions for MOSI With Respect to S_CLK

Knud Tangsgaard

Part Number: TRF7963A

Question regarding issue mentioned in: Application Report SLOA1408B, section 1.7: Timing Conditions for MOSI With Respect to S_CLK

I am using TRF7963A in SPI mode with SS

Is this issue relevant for TRF7963A?
Is this issue only relevant when SS active (TRF7963A)?
Or is it also relevant when communicating with other devices on SPI bus (when SS high)?
How to recover?
In case of ‘failure’, does TRF7963A switch back to SPI mode on next SPI chip select (SS high, SS low again)?

Regards Knud

23 days ago

0 Knud Tangsgaard 22 days ago

Prodigy 80 points

One more question:
Application note state, that problem does not occur if falling edge of SCLK and MOSI at same time.
In my opinion, does nothing occur at exact same time – there is always a small difference caused by PCB track length and/or small capacitance on PCB, etc.
To ensure error free operation, what is the exact timing requirement when using standard MCU SPI driver, where SCLK and MISO may fall at same time?

0 Rizwan Murji 3 days ago in reply to Knud Tangsgaard

TI__Genius 12960 points

The document SLOA140B applies to the non-A variants of the TRF796x family. For the -A family of variants, please refer to : https://www.ti.com/lit/an/sloa155/sloa155.pdf and in particular #7.

Thanks,

Riz

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TRF7963A: Timing Conditions for MOSI With Respect to S_CLK