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CC11xx PCB Layer Stack-Up Thickness

Other Parts Discussed in Thread: CC2430

The document swra168a mentions that CC11xx PCBs should have 0.8-1.0mm (~31-39mil) distance between the top layer (containing the RF section) and the 2nd layer (solid ground plane). The reference design for CC111x indicates that a 1.6mm (~62mil) thick FR-4 PCB should be used, however the PCB layer stack-up thicknesses are not mentioned (nor are any specific dielectric constants).

Since PCBs should be symmetrical, the distance between layers 3 and 4 should be the same as between layers 1 and 2, which is 0.8-1.0mm. However, with two 0.8mm cores and a prepreg layer, the total thickness exceeds the target 1.6mm.

The nearest component reference design with layer stack-up info is the reference design for CC2430. It indicates that the distance between layers 1 and 2 (and between 3 and 4) should be 0.35mm, which is a lot more reasonable for a final PCB thickness of 1.6mm.

Can anyone clarify the situation? Is it because swra168a uses 2-layer boards?

What are the ideal PCB layer stack-up thicknesses for the CC1111 915MHz reference design on a 1.6mm-thick 4-layer board?

Thank you,

Alex

  • Here are some numbers;

    FR-4 dielectric constant  =  Er  = 4.3 at 1GHz
    50 ohm microstrip line on FR-4 is line width / substrate height = w/h = 1.94

    The line width approaching the RF connector in the swra168a reference design is 1.3mm wide on a FR4 substrate.
    As measure on a Ti CC1110EM the substrate is .82mm thick giving a w/h = 1.6 which is a Zo of 56.1 ohms which is close enough to 50 ohms.

    The designer may have chosen this impedance to compensate for the capacitive antenna transition, also from the "Read Me" in the CC111x reference design notes it looks like Ti uses Er = 4.5 which would set Zo = 54 Ohms for 1.3mm/.8mm. 

    Q. Since PCBs should be symmetrical, the distance between layers 3 and 4 should be the same as between layers 1 and 2, which is 0.8-1.0mm. However, with two 0.8mm cores and a prepreg layer, the total thickness exceeds the target 1.6mm.

    If the cores are .8mm as suggested then the separation between the transmission line and ground plane (layer 1 & 2) is .8mm and the desired w/h is maintained. The thickness of the prepreg and 2nd core does not matter, nor does total thickness. But be careful here. Many quick turn shops (e.g. pcb123) put layer 2 & 3 on a .7mm core and layers 1 & 4 are applied to the prepreg which is only .3mm thick and have a Er slightly less than FR-4 (~3.8 - 4.0). If you put a two layer ref design on this you will have a 1.3mm line on a .3 thick dielectric which is a w/h of 4.3 or a Zo = 28 ohms which is getting into some serious mis-match. 

    Q. What are the ideal PCB layer stack-up thicknesses for the CC1111 915MHz reference design on a 1.6mm-thick 4-layer board?

    The  ideal PCB layer stack-up thickness is what is available from your supplier. The majority of the CC111x matching network is lumped element (Ls & Cs). With a thin (.3mm) dielectric the component pads and the line between them need to be sufficient to be reliable but no larger.  I have done 7 custom designs using 0402 size parts with good success at both 1 and 2.4GHz on .3mm layers. The 50 OHM transmission line to the RF connector needs to be w/h = 1.94. With a .3mm line to ground plane spacing this is a line width of .58mm.   Please note that with a largely lumped element design with the only distributed element being the transmission line to the antenna, errors in the range of +/- 10% are not going to push you off a cliff performance wise.

    Lines with no ground plane (i.e. only air) such as some antenna designs are fairly insensistive to substrate thickness and thinner is generally better so no change from the reference design is needed.

    Hope you did not want a short answer....

     

    The only CC11xx ref design I'm aware of is swrc112 which in the readme file states in is a two layer design on a .8 FR4 (Er=4.5) substrate.

  • Hi

    thanks for the detailed explanation, my follow up question is:

    basically lowering the dielectric material height means the width of the TL to the RF connector also should get lower,

    I'm asking if there is any other functional limit on the width of the TL to the ANT? (assuming 50ohm is taken care),

    i read that you've designed with h/w of 11.8/22.9mil.

    Question2

    what is the guidline with regards to the L & C connection TL of very short length?

    Best regards

  • Q.) basically lowering the dielectric material height means the width of the TL to the RF connector also should get lower,
    A.) True:  Over a fairly wide range the width/height ratio determines the line impedance and should be maintained.


    Q.) I'm asking if there is any other functional limit on the width of the TL to the ANT?
    A.) Regardless of w/h it is hard to get impedances below 20 ohms or much above 100 on micro-strip. If the line gets too narrow on very thin (<5 mil) substrates the loss goes up very quickly. If the line is very narrow or very wide the transition to component pads or other lines become tricky. Ideally you should have at least 2 h between the TL and the grounded fill (copper pour) but never less than 1 h. All of this applies while over the ground plane. Once on board material without a ground plane (such as a printed antenna) everything changes.

    Q.) what is the guideline with regards to the L & C connection TL of very short length?
    A.) I assume you mean between L and C components. As h gets smaller the component pads become more like shunt caps. The effect is small and will vary depending if it is a junction with a shunt cap where it is synergistic or between two series components. Best is to include the lines and pads in the circuit model, otherwise keep it clean and avoid step transitions (i..e very narrow lines to large pads).