CC1101 basic settings for TX and RX

Philippe CHAGNY

Other Parts Discussed in Thread: CC1101, TEST2

Hello all

I have buy some OEM CC1101 Chinese module on eBay and try to use it on my own devlopment board.

the SPI side is working fine. i can access to all registers.

i try to put one board in TX mode and send 10 bytes in loop, each seconds. and would like to receive it on the other board !

i request help because it's not working !i don't know if it send really, i don't know if the RX side that is faulty ...?

i don't have any spectrum analyzer to valide my TX side. only scope

i have search and search any tutorial. find some code but i'm not a C guru and work with BASIC language. so all is confuse, the codes samples are too much complicated.

i search the simplest tutorial to put a TX node and an RX node. to validate all the hardware / software side before do more stuff.

Please any CC1101 guru can help me ? point me on the simplest configuration ?

i try to use smartRF and don't find how create my own configuration. in the easy mode, there is 902, 868 and 433MHz. my module are tuned for 915MHz.

so i'm not sure about what i do :(

Please any help would be appreciate.. i turn around since 2 weeks !

Thanks for all suggestions, best regards

Phil

over 13 years ago

0 taylan mert over 13 years ago

Intellectual 270 points

Fullscreen 4657.CC1100-CC2500.c Download

//------------------------------------------------------------------------------
//  Description:  This file contains functions that configure the CC1100/2500
//  device.
//
//  Demo Application for MSP430/CC1100-2500 Interface Code Library v1.0
//
//  K. Quiring
//  Texas Instruments, Inc.
//  July 2006
//  IAR Embedded Workbench v3.41
//------------------------------------------------------------------------------


#include "include.h"
#include "TI_CC_CC1100-CC2500.h"

#define TI_CC_RF_FREQ  433                 // 315, 433, 868, 915, 2400



//------------------------------------------------------------------------------
//  void writeRFSettings(void)
//
//  DESCRIPTION:
//  Used to configure the CCxxxx registers.  There are five instances of this
//  function, one for each available carrier frequency.  The instance compiled
//  is chosen according to the system variable TI_CC_RF_FREQ, assigned within
//  the header file "TI_CC_hardware_board.h".
//
//  ARGUMENTS:
//      none
//------------------------------------------------------------------------------


#if TI_CC_RF_FREQ == 315                          // 315 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 315.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (1)  address check
// FIFO autoflush = 0
// Device address = 1
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,   0x0B); // GDO2 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,   0x06); // GDO0 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,   0xFF); // Packet length.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,     0x01); // Device address.
    TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,   0x00); // Channel number.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,  0x0B); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,    0x0C); // Freq control word, high byte
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,    0x1D); // Freq control word, mid byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,    0x89); // Freq control word, low byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,  0x2D); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,  0x3B); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,  0x73); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,   0x1D); // Freq Offset Compense. Config
    TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,    0x1C); //  Bit synchronization config.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT1, 0x31); 
    TI_CC_SPIWriteReg(TI_CCxxx0_WOREVT0, 0x6A);
    TI_CC_SPIWriteReg(TI_CCxxx0_WORCTRL, 0x38);
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,   0xB6); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,   0x10); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,   0xEA); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,    0x88); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,    0x31); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x51};
extern char paTableLen = 1;

#endif


#if TI_CC_RF_FREQ == 433                          // 433 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 433.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,   0x0B); // GDO2 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,   0x06); // GDO0 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,   0xFF); // Packet length.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,     0x01); // Device address.
    TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,   0x00); // Channel number.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,  0x0B); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,    0x10); // Freq control word, high byte
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,    0xA7); // Freq control word, mid byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,    0x62); // Freq control word, low byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,  0x2D); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,  0x3B); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,  0x73); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,   0x1D); // Freq Offset Compens. Config
    TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,    0x1C); //  Bit synchronization config.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,   0xB6); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,   0x10); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,   0xEA); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,    0x88); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,    0x31); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x51};
extern char paTableLen = 1;

#endif


#if TI_CC_RF_FREQ == 868                          // 868 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 868.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,   0x0B); // GDO2 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,   0x06); // GDO0 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,   0xFF); // Packet length.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,     0x01); // Device address.
    TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,   0x00); // Channel number.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,  0x0B); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,    0x21); // Freq control word, high byte
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,    0x62); // Freq control word, mid byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,    0x76); // Freq control word, low byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,  0x2D); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,  0x3B); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,  0x73); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 ,   0x3F); // MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 ,   0x18); // MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,   0x1D); // Freq Offset Compens. Config
    TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,    0x1C); //  Bit synchronization config.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,   0xB6); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,   0x10); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,   0xEA); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,    0x88); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,    0x31); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x60};
extern char paTableLen = 1;

#endif


#if TI_CC_RF_FREQ == 915                          // 915 MHz
// Product = CC1100
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 915.000000 MHz
// Channel spacing = 199.951172 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,   0x0B); // GDO2 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,   0x06); // GDO0 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,   0xFF); // Packet length.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05); // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,     0x01); // Device address.
    TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,   0x00); // Channel number.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,  0x0B); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,    0x23); // Freq control word, high byte
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,    0x31); // Freq control word, mid byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,    0x3B); // Freq control word, low byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,  0x2D); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,  0x3B); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,  0x73); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,   0x1D); // Freq Offset Compens. Config
    TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,    0x1C); //  Bit synchronization config.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,   0xB6); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,   0x10); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,   0xEA); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,    0x88); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,    0x31); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,    0x0B); // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0x50};
extern char paTableLen = 1;

#endif



#if TI_CC_RF_FREQ == 2400                          // 2.4GHz
// Product = CC2500
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2433.000000 MHz
// Channel spacing = 199.950000 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word.
// Packetlength = 255
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet
// GDO2 signal selection = (11) Serial Clock
void writeRFSettings(void)
{
    // Write register settings
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG2,   0x0B);  // GDO2 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_IOCFG0,   0x06);  // GDO0 output pin config.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTLEN,   0xFF);  // Packet length.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL1, 0x05);  // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_PKTCTRL0, 0x05);  // Packet automation control.
    TI_CC_SPIWriteReg(TI_CCxxx0_ADDR,     0x01);  // Device address.
    TI_CC_SPIWriteReg(TI_CCxxx0_CHANNR,   0x00); // Channel number.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL1,  0x07); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ2,    0x5D); // Freq control word, high byte
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ1,    0x93); // Freq control word, mid byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREQ0,    0xB1); // Freq control word, low byte.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG4,  0x2D); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG3,  0x3B); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG2,  0x73); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM1 ,   0x3F); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_MCSM0 ,   0x18); //MainRadio Cntrl State Machine
    TI_CC_SPIWriteReg(TI_CCxxx0_FOCCFG,   0x1D); // Freq Offset Compens. Config
    TI_CC_SPIWriteReg(TI_CCxxx0_BSCFG,    0x1C); //  Bit synchronization config.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND1,   0xB6); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FREND0,   0x10); // Front end RX configuration.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL3,   0xEA); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST2,    0x88); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST1,    0x31); // Various test settings.
    TI_CC_SPIWriteReg(TI_CCxxx0_TEST0,    0x0B);  // Various test settings.
}

// PATABLE (0 dBm output power)
extern char paTable[] = {0xFB};
extern char paTableLen = 1;

#endif


//-----------------------------------------------------------------------------
//  void RFSendPacket(char *txBuffer, char size)
//
//  DESCRIPTION:
//  This function transmits a packet with length up to 63 bytes.  To use this
//  function, GD00 must be configured to be asserted when sync word is sent and
//  de-asserted at the end of the packet, which is accomplished by setting the
//  IOCFG0 register to 0x06, per the CCxxxx datasheet.  GDO0 goes high at
//  packet start and returns low when complete.  The function polls GDO0 to
//  ensure packet completion before returning.
//
//  ARGUMENTS:
//      char *txBuffer
//          Pointer to a buffer containing the data to be transmitted
//
//      char size
//          The size of the txBuffer
//-----------------------------------------------------------------------------
char RFSendPacket(char *txBuffer, char size)
{ unsigned int hwfault=0;
  TI_CC_SPIWriteBurstReg(TI_CCxxx0_TXFIFO, txBuffer, size); // Write TX data
  TI_CC_SPIStrobe(TI_CCxxx0_STX);           // Change state to TX, initiating
                                            // data transfer

  while (!(TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN))
  {	hwfault++;
  	if(hwfault>=200)
  	{return 0;}
  }
  hwfault=0;                          // Wait GDO0 to go hi -> sync TX'ed
  while (TI_CC_GDO0_PxIN&TI_CC_GDO0_PIN);
  {	hwfault++;
  	if(hwfault>=200)
  	{return 0;}
  }                                          // Wait GDO0 to clear -> end of pkt
  TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN;      // After pkt TX, this flag is set.
  return 1;                                       // Has to be cleared before existing
}



//-----------------------------------------------------------------------------
//  char RFReceivePacket(char *rxBuffer, char *length)
//
//  DESCRIPTION:
//  Receives a packet of variable length (first byte in the packet must be the
//  length byte).  The packet length should not exceed the RXFIFO size.  To use
//  this function, APPEND_STATUS in the PKTCTRL1 register must be enabled.  It
//  is assumed that the function is called after it is known that a packet has
//  been received; for example, in response to GDO0 going low when it is
//  configured to output packet reception status.
//
//  The RXBYTES register is first read to ensure there are bytes in the FIFO.
//  This is done because the GDO signal will go high even if the FIFO is flushed
//  due to address filtering, CRC filtering, or packet length filtering.
//
//  ARGUMENTS:
//      char *rxBuffer
//          Pointer to the buffer where the incoming data should be stored
//      char *length
//          Pointer to a variable containing the size of the buffer where the
//          incoming data should be stored. After this function returns, that
//          variable holds the packet length.
//
//  RETURN VALUE:
//      char
//          0x80:  CRC OK
//          0x00:  CRC NOT OK (or no pkt was put in the RXFIFO due to filtering)
//-----------------------------------------------------------------------------
char RFReceivePacket(char *rxBuffer, char *length)
{
  char status[2];
  char pktLen;

  if ((TI_CC_SPIReadStatus(TI_CCxxx0_RXBYTES) & TI_CCxxx0_NUM_RXBYTES))
  {
    pktLen = TI_CC_SPIReadReg(TI_CCxxx0_RXFIFO); // Read length byte

    if (pktLen <= *length)                  // If pktLen size <= rxBuffer
    {
      TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, rxBuffer, pktLen); // Pull data
      *length = pktLen;                     // Return the actual size
      TI_CC_SPIReadBurstReg(TI_CCxxx0_RXFIFO, status, 2);
                                            // Read appended status bytes
      return (char)(status[TI_CCxxx0_LQI_RX]&TI_CCxxx0_CRC_OK);
    }                                       // Return CRC_OK bit
    else
    {
      *length = pktLen;                     // Return the large size
      TI_CC_SPIStrobe(TI_CCxxx0_SFRX);      // Flush RXFIFO
      return 0;                             // Error
    }
  }
  else
      return 0;                             // Error
}

8055.CC1100-CC2500.h 7534.definitions.h 7446.gen_func.h

Fullscreen 0383.gen_func.c Download

#include "include.h" 
#include "gen_func.h"


unsigned int read_flash (char segment)
{
	unsigned int code;
	unsigned int *p;
  	p = (unsigned int *)0x1000+segment;
  	code=*p;
  	return code;
}


void write_flash(char segment,unsigned int value)
{
  	unsigned int *Flash_ptr;                          // Flash pointer
  	unsigned int all_values[21];
	unsigned int i;
  	FCTL2 = FWKEY + FSSEL0 + FN1;		// MCLK/3 for Flash Timing Generator
	for(i=0;i<21;i++)
	{
		all_values[i]=read_flash(i);
	}
	all_values[segment]=value;
 	Flash_ptr = (unsigned int *)0x1000; // Initialize Flash pointer
  	FCTL3 = FWKEY;                      // Clear Lock bit
  	FCTL1 = FWKEY + ERASE;              // Set Erase bit, allow interrupts
  	*Flash_ptr = 0;                     // Dummy write to erase Flash segment
  	FCTL1 = FWKEY + WRT;                // Set WRT bit for write operation

	for(i=0;i<21;i++)
	{
    	*Flash_ptr++ = all_values[i];                   // Write value to flash
	}
	FCTL1 = FWKEY;                            // Clear WRT bit
	FCTL3 = FWKEY + LOCK;                     // Set LOCK bit
}

void display(char x)
{
	DISPLAY_PxOUT |=0x7F;
switch (x) 
{	
	case 0://0
		DISPLAY_PxOUT &=0xBF; //3F
		break;
	case 1://1
		DISPLAY_PxOUT &=0x86; //06
		break;
	case 2://2
		DISPLAY_PxOUT &=0xDB; //5B
		break;
	case 3://3
		DISPLAY_PxOUT &=0xCF; //4F
		break;
	case 4://4
		DISPLAY_PxOUT &=0xE6; //66
		break;
	case 5://5
		DISPLAY_PxOUT &=0xED; //6D
		break;
	case 6://6
		DISPLAY_PxOUT &=0xFD; //7D
		break;
	case 7://7
		DISPLAY_PxOUT &=0x87; //07
		break;
	case 8://8
		DISPLAY_PxOUT &=0xFF; //7F
		break;
	case 9://9
		DISPLAY_PxOUT &=0xEF; //6F
		break;
	case 'A'://A
		DISPLAY_PxOUT &=0xF7;// 77
		break;
	case 'B'://B
		DISPLAY_PxOUT &=0xFC;//7C
		break;
	case 'C'://C
		DISPLAY_PxOUT &=0xB9;//39
		break;
	case 'D'://d
		DISPLAY_PxOUT &=0xDE;//5E
		break;
	case 'E'://E
		DISPLAY_PxOUT &=0xF9;//79
		break;
	case 'F'://F
		DISPLAY_PxOUT &=0xF1;//71
		break;
	case 'P'://P
		DISPLAY_PxOUT &=0xF3;//73
		break;
	case ' '://Empty
		DISPLAY_PxOUT &=0x80;//00
		break;
	default:
		break;
}
}

void gezinen_cizgiler(void)
{
	char i;
	char x;
		for(i=0;i<=3;i++)// Panel ID �retildi�ini belirten, Ekranda gezinen �izgiler
		{
			x=1;
			while(x<127)
			{
				if(!(x==BIT6))
				{		
	  				DISPLAY_PxOUT =x;
	  				delay_ms(40);
				}
	  			x=x<<1;
			}		
		}		
}

void initialize_io(void)
{	
	BUTTON_PxDIR |= low_bat_cikis+supervision_cikis;
  	BUTTON_PxOUT |= BUTTON_SW1+BUTTON_SW2;
  	BUTTON_PxREN |= BUTTON_SW1;
  	BUTTON_PxREN |= BUTTON_SW2;
    BUTTON_PxOUT&=~(low_bat_cikis+supervision_cikis);//sondurur
  	
	Alarm_DIR &=~(alarm_high+alarm_low+arm_high+arm_low); 
  	Alarm_OUT |= alarm_low+arm_low;			//pull up
  	Alarm_OUT &=~(alarm_high+arm_high);		//pull down
  	Alarm_REN |= alarm_high + alarm_low + arm_high + arm_low ;
	
	DISPLAY_PxDIR = 0XFF;
	DISPLAY_PxOUT = 0X00;

  	LED_PxSEL = 0x00;
  	LED_PxOUT = 0x00; 
	LED_PxDIR |= DL1 + DL2 + DL3 + DL4;
	
	//WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  	//BCSCTL1 = CALBC1_1MHZ;                    // Set DCO
  	//DCOCTL = CALDCO_1MHZ;						// 
  	//P3SEL = 0x30;                             // P3.4,5 = USCI_A0 TXD/RXD
  	//UCA0CTL1 |= UCSSEL_2;                     // SMCLK
  	//UCA0BR0 = 8;                              // 1MHz 9600
  	//UCA0BR1 = 0;                              // 1MHz 9600
  	//UCA0MCTL = UCBRS2 + UCBRS0;               // Modulation UCBRSx = 1
  	//UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
}

void initialize_RF(void)
{
	TI_CC_SPISetup();                         // Initialize SPI port
	TI_CC_PowerupResetCCxxxx();               // Reset CCxxxx
	
	writeRFSettings();                        // Write RF settings to config reg
	
	TI_CC_SPIWriteBurstReg(TI_CCxxx0_PATABLE, paTable, paTableLen);//Write PATABLE
	
	TI_CC_GDO0_PxIES |= TI_CC_GDO0_PIN;       // Int on falling edge (end of pkt)
	TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN;      // Clear flag
	TI_CC_GDO0_PxIE |= TI_CC_GDO0_PIN;        // Enable int on end of packet
	
	TI_CC_SPIStrobe(TI_CCxxx0_SRX);           // Initialize CCxxxx in RX mode.
}
void delay_ms(unsigned int n)
{
	unsigned int x;
	unsigned int tw;
	x=0;
	tw=93*n;
  	while(x < tw){WDTCTL = WDTPW + WDTCNTCL;
	x++;}
}
unsigned long InitSeed(void)
{
	NextVal();
	NextVal();
	NextVal();
	return NextVal();
}
unsigned long NextVal(void)
{
 Seed=Seed*1664525L+1013904223L;
 return Seed;
}
char Button_Hold_Time(void)
{
	unsigned int sn=2500;			   		// Bas�l� tutma s�resi 2500 =5sn
	unsigned int hold_time_h=0;	// Button press time holder high
	unsigned int hold_time_l=0;	// Button press time holder low	
	
	if (!(BUTTON_SW2 & BUTTON_PxIN))
	{
		LED_PxOUT= DL1 + DL2 + DL3 + DL4;
		while(!(BUTTON_SW2 & BUTTON_PxIN))
		{		
			hold_time_l++;
			//if(hold_time_l>=65530)
			if(hold_time_l>=100)
			{
				hold_time_h++;
				hold_time_l=0;
			}
			if(hold_time_h>=sn)
			{
				LED_PxOUT&=0xE1;
				break;
			}
		}
		LED_PxOUT=0x00;
		if(hold_time_h>=sn)
		return 1;
		else if(hold_time_h>=1)
		return 2;	
		else return 0;		
	}
	else
	{
		return 0;
	}
}

void ignore_signal(void)
{
	LED_PxOUT=DL1+DL2+DL3+DL4;
	delay_ms(300);
	LED_PxOUT=0x00;
	delay_ms(300);
	LED_PxOUT=DL1+DL2+DL3+DL4;
	delay_ms(300);
	LED_PxOUT=0x00;
	delay_ms(300);
}

2262.include.h

Fullscreen 4721.main.c Download

#include "include.h"
#include "definitions.h"
#include "gen_func.h"

#include "stdlib.h"
char programming_mode(void);
char program_mode=0;
void check_Siren_Reg(void);
void check_Tamper_State(void);
void acilis_siren_kontrol(void);
void check_supervise(void);
void check_armed(void);
void check_alarm(void);
char check_receive (char frst_data,char scnd_data);
void clear_rxBuffer (void);
char elektrik_gitti_geldi=1;
unsigned int Panel_ID=0;
char Panel_ID_L=35;
char Panel_ID_H=35;
char Siren_ID_L=20;
char Siren_ID_H=20;
char s_reg=0;
char ayni_siren_degil=1;
unsigned int Siren_ID_aynimi[4]={1,2,3,4};
int k=0;//ske//ayn� sireni kaydetmesin diye kullan�lacak.
char Siren_Sum=0;
char t=0;
char sr=0;
char dis=0;
char statebat=0;
char statesv=0;
char staterole=0;
char Reg_Siren_D=0;
char programing_state=0;
unsigned int Siren_ID[4]={10,10,10,10};
unsigned int siren_acilis_durum[4]={0,0,0,0};
unsigned int Siren_Supervise[4]={0,0,0,0};
unsigned int Supervise_durum[4]={1,1,1,1};//sirenle haberle�ilebiliyorsa 1, haberle�ilemiyorsa 0 .
unsigned int mesok[4]={0,0,0,0};
void check_ID(void);
char disp_siren=0;
unsigned int PANREGOK=0;
unsigned int taylan1=0;
unsigned int Supervise_Duration=10;//600sn do�rusu 
unsigned int reg_timeout=0;
char send_count=0;
char kontrol=0;
unsigned int  Siren_IDr=0;
unsigned int siren_tamper_var[4]={0,0,0,0};//ske
unsigned int si_tamp_var=0;
unsigned int siren_low_bat_var[4]={0,0,0,0};//ske
char sil=0;
unsigned int Data1;
unsigned int Data2;
unsigned int Data3;
unsigned int Data4;
unsigned int Data5;
unsigned int rxBuffer_5_depo;
unsigned int Data6;
unsigned int Data7;
unsigned int Data8;
char txsicaklik=0;
unsigned int txsay=0;
char button_state=0;
char alarm_in=0;//ilk a��l��ta alarm yoksa sirenler alarmda olursa alarm durdurma yollas�n diye 1 yap�ld�
char arm_in=0;
char role_kapatma=1;//tamper� aktif pasif yapmak i�in kullan�l�yor
char alarm_test=0;
char testsw=0;
char testbat=0;
unsigned int hold_time1=0;
unsigned int hold_time2=0;
unsigned int new_siren_falult=0;
unsigned int hold_time_lsw1=0;
unsigned int hold_time_hsw1=0;

unsigned int hold_time_hon=0;//  Button press time holder high
unsigned int hold_time_lon=0;//  Button press time holder low	
unsigned int hold_time_hoff=0;// Button press time holder high
unsigned int hold_time_loff=0;// Button press time holder low	

unsigned int hold_time_h_for_low=0;// Button press time holder high
unsigned int hold_time_l_for_low=0;// Button press time holder low	
unsigned int hold_time_h_for_high=0;// Button press time holder high
unsigned int hold_time_l_for_high=0;// Button press time holder low	

int sk=0;
int sk1=0;
int ask=0;
int bsk=0;
unsigned int qtime=0;
unsigned int dataready;
unsigned int comok=20;
unsigned int comf=0;
unsigned int ressay=0;
unsigned int nocom=0;
unsigned int rec_timeout=0;//receive check timeout
unsigned int rec_timeout2=0;//receive check timeout
unsigned int comtime=0;
unsigned int noalmarm=0;
unsigned int quickly=0;
unsigned int qstate1=0;
unsigned int qstate2=0;
unsigned int mesokres=0;
/////////////////////////////////////////////////////////////////////////////////////
//				          Kablosuz Siren Panel Taraf� Program�                     //
//                                                                                 //
//                          Flash'a kaydedile Veri tablosu...                      //
//       _____________________________________________________________________     //
//		| Segment S�ras� |  De�i�ken Ad�  |     G�revi          |   De�eri    |    //
//      |---------------------------------|---------------------|-------------|    //
//      |     ( 0 )      |                | ID Kayd� Yap�ld�    |     0x0D    |    //
//      |     ( 1 )      |  Panel_ID      | Random Unique ID    |             |    //
//      |     ( 2 )      |  Siren_Sum     | Kay�tl� siren Adedi |             |    //
//      |     ( 3 )      |  Siren_ID[0]   | 1.Siren ID          | Min:0 Max:8 |    //
//      |     ( 4 )      |  Siren_ID[1]   | 2.Siren ID          |             |    //
//      |     ( 5 )      |  Siren_ID[2]   | 3.Siren ID          |             |    //
//      |     ( 6 )      |  Siren_ID[3]   | 4.Siren ID          |             |    //
//      |     ( 7 )      |  Siren_ID[4]   | 5.Siren ID          |             |    //
//      |     ( 8 )      |  Sire... [.]   |      ...            |             |    //
//      |      ...       |      ...       |      ...            |             |    //
//      |     ( 19 )     |  Siren_ID[7]   | 8.Siren ID          |             |    //
//      |________________|________________|_____________________|_____________|    //
//                                                                                 //
/////////////////////////////////////////////////////////////////////////////////////
void main (void) 
{
	WDTCTL = WDT_MRST_32;
	//WDTCTL = WDTPW + WDTHOLD; 
	BUTTON_PxOUT&=~supervision_cikis;
    BUTTON_PxOUT&=~low_bat_cikis;
	initialize_io();
	initialize_RF();
	delay_ms(600);
	initialize_RF();//elek. geldi�inde cc1100 den dolay� kitleniyordu.Bu kitlenmeyi engellemek i�in kondu.
	WDTCTL = WDTPW + WDTCNTCL;
	check_ID();	// ilk a��l�� m�?	 				
	check_Siren_Reg();			// kaydelimi� siren adedini oku ve kay�tl� sirenlerin bilgilerini al.
	display(Siren_Sum); 		// kaydelimi� siren adedi g�ster.

	

	while(1)
	{	
		if(comtime<=3)	
		{   
	        Siren_ID_L=0x00FF&Siren_ID[sr];
	        Siren_ID_H=(0xFF00&Siren_ID[sr])>>8;		        		   
			rec_timeout=0;
	        rec_timeout2=0;           		    
	    	__bic_SR_register( GIE ); 	// Disable interrupts
			delay_ms(10);		
			txBuffer[0] = 7;        	// Packet length
			txBuffer[1] = 0x01;     	// Packet address
	 	    txBuffer[2] = Siren_ID_H;;						
		   	txBuffer[3] = Siren_ID_L;;			
			txBuffer[4] = Panel_ID_H; 	// Alarm datas� 0x07
			txBuffer[5] = Panel_ID_L;
			if((siren_tamper_var[0]+siren_tamper_var[1]+siren_tamper_var[2]+siren_tamper_var[3])>0)
			{si_tamp_var=1;}
			else{si_tamp_var=0;}
			txBuffer[6] = si_tamp_var;
			if(RFSendPacket(txBuffer, 8)==0)
			{taylan1=20;TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN;}  // Send value over RF
		   	else
		   	{taylan1=15;}		   	
		   	delay_ms(10);
		   	__bis_SR_register( GIE ); 	// Enable interrupts
			dataready=0;	    
	        //__bis_SR_regsiter(LPM1_BITS | GIE);    
			while((dataready==0))
			{ rec_timeout++;delay_ms(1);
			  if(rec_timeout>=40){dataready=85;}
			}		
			delay_ms(20);
		}	
			if(dataready==55 )
			{	
								
				if(rxBuffer[6]==0x0D && rxBuffer[1]==Panel_ID_H && rxBuffer[2]==Panel_ID_L)
				{   
					Siren_ID_L=0x00FF&Siren_ID[sr];
	                Siren_ID_H=(0xFF00&Siren_ID[sr])>>8;
                    if((Siren_ID_H==rxBuffer[3])&&(Siren_ID_L==rxBuffer[4]))
                    {	program_mode=0;new_siren_falult=0;//comtime=4;
						//Supervise_durum[sr]=1;
						Siren_Supervise[sr]=0;	
						if(quickly==1)
						{mesok[sr]=1;}
						if((mesok[0]+mesok[1]+mesok[2]+mesok[3])>=Siren_Sum)
						{mesok[0]=0;mesok[1]=0;mesok[2]=0;mesok[3]=0;quickly=0;}														
						siren_acilis_durum[sr]=rxBuffer[5]; 
						if(siren_acilis_durum[sr]==8){ siren_low_bat_var[sr]=0;siren_tamper_var[sr]=0;}//sirende herhangi bir  durum yok.�imdilik bir�ey yap�lm�yacak.
						//if(siren_acilis_durum[sr]==4){ }//siren panel alarm durumunda �imdilik bir�ey yap�lm�yacak.
						if(siren_acilis_durum[sr]==3)
						{siren_low_bat_var[sr]=1;siren_tamper_var[sr]=1;rxBuffer[5]=0;}
						if(siren_acilis_durum[sr]==2){siren_low_bat_var[sr]=1;}//siren low_batary durumunda.	
						if(siren_acilis_durum[sr]==1)
						{
							rxBuffer[5]=0;
							siren_tamper_var[sr]=1;
						}
						if(siren_acilis_durum[sr]==250)
						{Supervise_durum[sr]=0;testsw=1;}
						else{
							 if(testsw==1)
							 {	testsw=0;
							 	Supervise_durum[0]=1;
							 	Supervise_durum[1]=1;
							 	Supervise_durum[2]=1;
							 	Supervise_durum[3]=1;
							 }
							}
						if(siren_acilis_durum[sr]==249)
						{siren_low_bat_var[sr]=1;testbat=1;}
						else{
								if(testbat==1)
								{testbat=0;
								 siren_low_bat_var[0]=0;
								 siren_low_bat_var[1]=0;
								 siren_low_bat_var[2]=0;
								 siren_low_bat_var[3]=0;
								}						
							}					
                    }
                    if((rxBuffer[5]==1)&&(comtime>=3))
                    {   if((siren_tamper_var[0]+siren_tamper_var[1]+siren_tamper_var[2]+siren_tamper_var[3])==0)
                    	comtime=1000;}                  
				}
				else if((rxBuffer[6]==0x76)&&(program_mode))
				{	if(Siren_Sum<=3)
					{	
						Siren_ID_H = rxBuffer[3];
						Siren_ID_L = rxBuffer[4];
						Siren_IDr=Siren_ID_L;
				    	Siren_IDr|=Siren_ID_H<<8;
						if((Siren_IDr!=Siren_ID[0])&&(Siren_IDr!=Siren_ID[1])&&(Siren_IDr!=Siren_ID[2])&&(Siren_IDr!=Siren_ID[3]))
						{Siren_Sum++;
						Siren_ID[Siren_Sum-1]=Siren_IDr;
				    	WDTCTL = WDTPW + WDTCNTCL;
						write_flash((Siren_Sum+2),Siren_ID[Siren_Sum-1]);
						sr=Siren_Sum-1;
						WDTCTL = WDTPW + WDTCNTCL;
						write_flash(2,Siren_Sum);
						}
					}
					program_mode=2;
					txBuffer[7] = 0xDD;					
				}
				rxBuffer[0]=0;rxBuffer[1]=0;rxBuffer[2]=0;rxBuffer[3]=0;rxBuffer[4]=0;
				rxBuffer[5]=0;rxBuffer[6]=0;comok=10;comf=0;nocom=0;ressay=0;
			}
			else 
			{	
				rxBuffer[0]=0;rxBuffer[1]=0;rxBuffer[2]=0;rxBuffer[3]=0;
				rxBuffer[4]=0;rxBuffer[5]=0;rxBuffer[6]=0;
				if(program_mode==1)
				{
					new_siren_falult++;
					if(new_siren_falult>=100)
					{program_mode=0;new_siren_falult=0;}
				
				}
				if(sr<Siren_Sum)
				{	comok=5;comf++;				
					if(comf>=5)
	    			{	comf=0;
	        			ressay++;
	        			if(ressay>=2)
	        			{	   
	        				nocom++;
	        				if(nocom>=20)
	        				{	
	        					nocom=0;
	        					__bic_SR_register( GIE );
	        					ressay=0;	        	
	        					initialize_RF();
	        					__bis_SR_register( GIE );    
	        				}     	
	        			}
	    			}
					if(comtime>=997)	
					{	Siren_Supervise[sr]++;
						if(Siren_Supervise[sr]>=100)
						{	Supervise_durum[sr]=0;
							Siren_Supervise[sr]=0;
						}
					}
				}
			}		 	
		    if(Supervise_durum[sr]==1)
		    {
		        LED_PxOUT&=~DL2;//led soner
				statesv=1;
				for (i = 0; i < Siren_Sum; ++i) 
			    {if(Supervise_durum[i]==0)statesv=0;}	
			    
			     if(statesv==1)BUTTON_PxOUT&=~supervision_cikis;	        
			     if(siren_tamper_var[sr]==1){LED_PxOUT|=DL1;DISPLAY_PxOUT|=tamp_relay;}//roleyi aktif eder.//LED YANAR
			     else
			     {  LED_PxOUT&=~DL1;//led soner
				    role_kapatma=1;
				    for (i = 0; i < Siren_Sum; ++i) 
			        {if(siren_tamper_var[i]==1)role_kapatma=0;	}	
			        if(role_kapatma==1)
			        {DISPLAY_PxOUT &=~ tamp_relay;}
			     }
			     if(siren_low_bat_var[sr]==1){LED_PxOUT|=DL3;BUTTON_PxOUT|=low_bat_cikis;}//sondurur//LED YANAR
			     else 
			     {	LED_PxOUT&=~DL3;	     
				    statebat=1;
				    for (i = 0; i < Siren_Sum; ++i) 
			        {if(siren_low_bat_var[i]==1)statebat=0;}	
			        if(statebat==1)BUTTON_PxOUT&=~low_bat_cikis;			     
			     }
		    }
		    else 
		    {LED_PxOUT|=DL2;LED_PxOUT&=~DL3;LED_PxOUT&=~DL1;BUTTON_PxOUT|=supervision_cikis;//BUTTON_PxOUT&=~low_bat_cikis;
		    }
			if((Supervise_durum[sr]==0)||(siren_tamper_var[sr]==1)||(siren_low_bat_var[sr]==1))LED_PxOUT|=DL4;
			else LED_PxOUT&=~DL4;
			if(alarm_test==0)					  
    		{check_armed();		//  txBuffer[7] = 0xAC;//S�RENE ARM KURULDU DATASI		
		    check_alarm();  	//	txBuffer[7] = 0x07;	alarm var,	0xF8; alarm yok
    		}
    		if(quickly==1)
    		{
    			qtime++;
    			if(qtime>=100)
    			{qtime=0;quickly=0;}
    		}
    		//buton 1 bas�ld� i�lemleri
		    if(!(BUTTON_SW1 & BUTTON_PxIN)&&(BUTTON_SW2 & BUTTON_PxIN))
		  	{		
				hold_time1++;
				if(hold_time1>=10)
				{   				
					hold_time1=50;  
					if(program_mode!=2)
					{                  					
						program_mode=1;
						LED_PxOUT =DL1+DL2+DL3+DL4;
						txBuffer[7] = 0x81;comtime=0;
						display(Siren_Sum);
					}
				}		
			}
			else{hold_time1=0;}
			
			//buton 2 bas�ld� i�lemleri
		    if(!(BUTTON_SW2 & BUTTON_PxIN))
		  	{		
				hold_time2++;
				if(hold_time2>=100)
				{   if(!(BUTTON_SW1 & BUTTON_PxIN))
					{hold_time2=600;
					Siren_ID_H = 0;
					Siren_ID_L = 0;
					Siren_ID[0]= 0;
					Siren_ID[1]= 0;
					Siren_ID[2]= 0;
					Siren_ID[3]= 0;
				   	WDTCTL = WDTPW + WDTCNTCL;
					write_flash(3,0);WDTCTL = WDTPW + WDTCNTCL;
					write_flash(4,0);WDTCTL = WDTPW + WDTCNTCL;
					write_flash(5,0);WDTCTL = WDTPW + WDTCNTCL;
					write_flash(6,0);
					i=0;sr=0;
					program_mode=0;
					Siren_Sum=0;
					WDTCTL = WDTPW + WDTCNTCL;
					write_flash(2,0);
					display(Siren_Sum);
					siren_tamper_var[0]=0;
					siren_tamper_var[1]=0;
					siren_tamper_var[2]=0;
					siren_tamper_var[3]=0;
					Supervise_durum[0]=1;
					Supervise_durum[1]=1;
					Supervise_durum[2]=1;
					Supervise_durum[3]=1;
					siren_low_bat_var[0]=0;
					siren_low_bat_var[1]=0;
					siren_low_bat_var[2]=0;
					siren_low_bat_var[3]=0;
					quickly=0;
					}
					else
					{txBuffer[7] = 0x07;alarm_test=1;quickly=1;}
				}
			}
			else
			{if(alarm_test==1){txBuffer[7] = 0xF8;}alarm_test=0;hold_time2=0;}
			
			
			WDTCTL = WDTPW + WDTCNTCL;	
			
			comtime++;delay_ms(2);
			if((quickly==1)&&(comtime>3))
		    {comtime=1000;}
			if((comtime>=1000))
			{	
				comtime=0;
	
	         		if(Siren_Sum!=0)
	         		{	sr++;
	         			if(sr>=4){sr=0;}
	         			if(sr>=Siren_Sum)
	         			{   DISPLAY_PxOUT |=0x7F;
	         				if(sr==1){DISPLAY_PxOUT &=129;}
	         				if(sr==2){DISPLAY_PxOUT &=192;}
	         				if(sr==3){DISPLAY_PxOUT &=136;}
	         			}	
	         			else
	         			{display(sr+1);}
	         		
	         		}

			}				   		    		    
	}			
//******************************************************************************	
//******************************************************************************	
}

void check_ID(void)
{

	PANREGOK=read_flash(0);		//panel register ok?
	if( !(PANREGOK==0x0D) )
	{	WDTCTL = WDTPW + WDTCNTCL;	 
		InitSeed();
	  	srand(NextVal());
	  	Panel_ID=rand();
	  	Panel_ID_L = 0x00FF & Panel_ID;
	  	Panel_ID_H = Panel_ID>>8;
	  	write_flash(0,0x0D);	// Panel Kayd� ger�ekle�tirildi
	  	WDTCTL = WDTPW + WDTCNTCL;
	  	write_flash(1,Panel_ID);
	  	DISPLAY_PxOUT &= 0x80;  	
		gezinen_cizgiler();	  	
	}
	else
	{	WDTCTL = WDTPW + WDTCNTCL;
	 	Panel_ID=read_flash(1);
	  	Panel_ID_L = 0x00FF & Panel_ID;
	  	Panel_ID_H = Panel_ID>>8;
	}
}




void check_armed(void)
{
	if((!(Alarm_IN&arm_low)||(Alarm_IN&arm_high))&&(arm_in==0))//arm aktif
	{	
		hold_time_h_for_high=0;
		hold_time_l_for_high=0;
		hold_time_l_for_low++;
		if(hold_time_l_for_low>=3)
		{	
			hold_time_l_for_low=0;
			hold_time_h_for_low++;
		}
		if(hold_time_h_for_low>=1)
		{
			hold_time_h_for_low=0;arm_in=1;
			txBuffer[7] = 0xAC;//S�RENE ARM KURULDU DATASI		
			quickly=1;qstate1=1;	
		}	
	}
	else if((!(Alarm_IN&arm_high)&&(Alarm_IN&arm_low))&&(arm_in==1))// arm pasif
	{	
		hold_time_h_for_low=0;
		hold_time_l_for_low=0;
		hold_time_l_for_high++;
		if(hold_time_l_for_high>=3)
		{
			hold_time_l_for_high=0;
			hold_time_h_for_high++;
		}
		if(hold_time_h_for_high>=1)
		{	hold_time_h_for_high=0;arm_in=0;txBuffer[7] = 0xDD;
			quickly=1;	qstate1=1;	
		}	
	}			
	else 
	{
		hold_time_h_for_low=0;// Button press time holder high
    	hold_time_l_for_low=0;// Button press time holder low	
    	hold_time_h_for_high=0;// Button press time holder high
    	hold_time_l_for_high=0;// Button press time holder low	
    	if(qstate1)
    	{
    		noalmarm++;
    		if(noalmarm>=150)
    		{noalmarm=0;qstate1=0;quickly=0;}
    	
    	}
    	
	}
}

void check_alarm(void)
{	
	if((!(Alarm_IN&alarm_low)||(Alarm_IN&alarm_high))&&(alarm_in==0))
	{
		hold_time_hoff=0;// Button press time holder high
		hold_time_loff=0;// Button press time holder low	
		hold_time_lon++;
		if(hold_time_lon>=3)
		{
			hold_time_lon=0;
			hold_time_hon++;
		}
		if(hold_time_hon>=1)
		{   
			hold_time_hon=0;
			alarm_in=1;
			txBuffer[7] = 0x07;	
			quickly=1;	qstate2=1;		
		}
	}
	else if(((Alarm_IN&alarm_low)&&!(Alarm_IN&alarm_high))&&(alarm_in==1))
	{
	       	hold_time_hon=0;// Button press time holder high
	       	hold_time_lon=0;// Button press time holder low	
			hold_time_loff++;
			if(hold_time_loff>=3)
			{
				hold_time_loff=0;
				hold_time_hoff++;
			}
			if(hold_time_hoff>=1)
			{	hold_time_hoff=0;
				alarm_in=0;
				txBuffer[7] = 0xF8;	
				quickly=1;	qstate2=1;	
			} 
	}
	else
	{
		hold_time_hon=0;// Button press time holder high
	    hold_time_lon=0;// Button press time holder low	
	    hold_time_hoff=0;// Button press time holder high
	    hold_time_loff=0;// Button press time holder low
    	if(qstate2)
    	{
    		noalmarm++;
    		if(noalmarm>=150)
    		{noalmarm=0;qstate2=0;quickly=0;}
    	
    	}	    	    
	}
}



   

void check_Siren_Reg(void)
{   
	Siren_Sum=read_flash(2);
	if(Siren_Sum>4)Siren_Sum=0;
	for(i=0;i<Siren_Sum;i++)
	{
		Siren_ID[i]=read_flash(3+i);
	}	
}



void check_Tamper_State(void)
{
	char tamp_state=0;
	for(i=0;i<Siren_Sum;i++)	
		if(siren_Alarm[i]&BIT0)
		tamp_state++;
		if(tamp_state>0)
		DISPLAY_PxOUT |= tamp_relay;
		else
		DISPLAY_PxOUT &= ~tamp_relay;
}

#pragma vector=PORT2_VECTOR
__interrupt void port2_ISR (void)
{
	
	if(P2IFG & TI_CC_GDO0_PIN)
	{sk=sk+1;
    	char len=7;                         // Len of pkt to be RXed (only addr
	                                        // plus data; size byte not incl b/c
	                                     	// stripped away within RX function)
	if (RFReceivePacket(rxBuffer,&len))		// Fetch packet from CCxxxx
     {  dataready=55; 
		Data1 = rxBuffer[0];        
    	Data2 = rxBuffer[1];
    	Data3 = rxBuffer[2];
    	Data4 = rxBuffer[3];
    	Data5 = rxBuffer[4];
    	Data6 = rxBuffer[5];
    	Data7 = rxBuffer[6];
    	Data8 = rxBuffer[7]; 	 
     }
     else 
     {dataready=65;//rxBuffer[6]=0;sk1=sk1+1;initialize_RF();
     }
     //if((rxBuffer[6]!=0x07)&&(rxBuffer[6]!=0xF8)&&(rxBuffer[6]!=0x0D)&&(rxBuffer[6]!=3)){rxBuffer[6]=0;initialize_RF();}// ba�ka veriler gelirse bufer� siler
     //	TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN;   
  	}
  	else{dataready=75;}
 	TI_CC_GDO0_PxIFG &= ~TI_CC_GDO0_PIN;  	
}

2117.msp430f2132.h 3113.TI_CC_CC1100-CC2500.h 6283.TI_CC_hardware_board.h 4061.TI_CC_msp430.h 1488.TI_CC_spi.c 7002.TI_CC_spi.h

You can use this files.They my own project. You can modify what to want.

0 TA12012 over 13 years ago

TI__Mastermind 36395 points

Phil,

I recommend using a register called MARCSTATE for your initial debug and you can use this both on the TX and the RX side.

TX side:

Issue SIDLE command

Check number of bytes in TXFIFO,

if more than 0 then Flush TXFIFO

Fill TX FIFO with data

Issue STX command, that is it.

Now, you can call MARCSTATE (repeatedly and quickly) to see the internal statemachine go thru the differnt steps of sending data.

RX side:

Issue SIDLE command

Check number of bytes in RXFIFO,

if more than 0 then Flush RXFIFO

Issue SRX command, that is it.

Now, you can call MARCSTATE (repeatedly and quickly) to see the internal statemachine go thru the differnt steps of sending data.

I hope this helps.

Regards,
/TA

0 Philippe CHAGNY over 13 years ago in reply to TA12012

Prodigy 120 points

Hi guys,

Taylan, thanks for your files, i will check your files.

TA12012, big thanks too, this is what i expected as answer. i will test the MARCSTATE as soon as my kids let me some time to play with my toys ! :)

does the init config different for the TX and the RX node ? or does i simply write all registers that are given by smartRF ?

but i would like to be sure that the registers i try to write are goods. please can you share a working configuration for 915MHz, from smartRF ?

i don't understand how to create my own "config" in smartRF. in easymode, i see 3 configurations. i would like to add my own config ..?

thanks guys, i will reply asap with my result tests.

have a nice day, regards

phil

0 Philippe CHAGNY over 13 years ago in reply to Philippe CHAGNY

Prodigy 120 points

Well, TA12012, i try to work first on the TX side.

here is my main code :

***********************************************************************************************

' Main program main:

Init_CPU()

DebugString_UART1("INIT CPU DONE")

CC1101_Reset()

DebugString_UART1("RESET CC1101 DONE")

CC1101_SetDefaultRegs()

CC1101_SetRegsFromsmartRF()

CC1101_SetRegsFromsmartRF_EKO()

CC1101_WriteBurstReg(CC1101_PATABLE, CC1101_PATABLE_0dBm, 8)

CC1101_DumpAllRegisters()

DebugValue_UART1("CC1101_PATABLE(0) : 0x", CC1101_ReadReg(CC1101_PATABLE)) '

DebugValue_UART1("PARTNUM = 0x", CC1101_ReadStatus(CC1101_PARTNUM))

DebugValue_UART1("VERSION = 0x", CC1101_ReadStatus(CC1101_VERSION))

newtx:

CC1101_WriteCdeStrobe(CC1101_SIDLE)

delay_ms(100)

DebugValue_UART1("CC1101_MARCSTATE : 0x", CC1101_ReadReg(CC1101_MARCSTATE))

stockebyte = CC1101_ReadStatus(CC1101_TXBYTES) and BYTES_IN_TXFIFO

if stockebyte > 0 then

DebugValue_UART1("TXFIFO NOT EMPTY : 0x", stockebyte)

CC1101_WriteCdeStrobe(CC1101_SIDLE)

CC1101_WriteCdeStrobe(CC1101_SFTX)

end if

for index = 0 to 9

CC1101.TXdata[index] = index

next index

CC1101_WriteBurstReg(CC1101_TXFIFO, CC1101.TXdata, 10)

CC1101_WriteCdeStrobe(CC1101_STX)

while true

stockebyte = CC1101_ReadReg(CC1101_MARCSTATE)

DebugValue_UART1("CC1101_MARCSTATE : 0x", stockebyte)

if stockebyte = 0x14 then

DebugString_UART1("TX DONE")

break

end if

wend

delay_ms (1000)

goto newtx

***********************************************************************************************

and here it is the debug terminal :

INIT CPU DONE<LF><CR>

Test CC1101 v1.00<LF><CR>

RESET CC1101 DONE<LF><CR>

*************************************<LF><CR>

Dump CC1101 registers<LF><CR>

CC1101_IOCFG2 : 0x0B<LF><CR>

CC1101_IOCFG1 : 0x2E<LF><CR>

CC1101_IOCFG0 : 0x06<LF><CR>

CC1101_FIFOTHR : 0x07<LF><CR>

CC1101_SYNC1 : 0xB5<LF><CR>

CC1101_SYNC0 : 0x47<LF><CR>

CC1101_PKTLEN : 0xFF<LF><CR>

CC1101_PKTCTRL1 : 0x05<LF><CR>

CC1101_PKTCTRL0 : 0x05<LF><CR>

CC1101_ADDR : 0x01<LF><CR>

CC1101_CHANNR : 0x00<LF><CR>

CC1101_FSCTRL1 : 0x0B<LF><CR>

CC1101_FSCTRL0 : 0x00<LF><CR>

CC1101_FREQ2 : 0x23<LF><CR>

CC1101_FREQ1 : 0x31<LF><CR>

CC1101_FREQ0 : 0x3B<LF><CR>

CC1101_MDMCFG4 : 0x2D<LF><CR>

CC1101_MDMCFG3 : 0x3B<LF><CR>

CC1101_MDMCFG2 : 0x73<LF><CR>

CC1101_MDMCFG1 : 0x22<LF><CR>

CC1101_MDMCFG0 : 0xF8<LF><CR>

CC1101_DEVIATN : 0x00<LF><CR>

CC1101_MCSM2 : 0x07<LF><CR>

CC1101_MCSM1 : 0x3F<LF><CR>

CC1101_MCSM0 : 0x18<LF><CR>

CC1101_FOCCFG : 0x1D<LF><CR>

CC1101_BSCFG : 0x1C<LF><CR>

CC1101_AGCCTRL2 : 0xC7<LF><CR>

CC1101_AGCCTRL1 : 0x00<LF><CR>

CC1101_AGCCTRL0 : 0xB2<LF><CR>

CC1101_WOREVT1 : 0x87<LF><CR>

CC1101_WOREVT0 : 0x6B<LF><CR>

CC1101_WORCTRL : 0xFB<LF><CR>

CC1101_FREND1 : 0xB6<LF><CR>

CC1101_FREND0 : 0x10<LF><CR>

CC1101_FSCAL3 : 0xEA<LF><CR>

CC1101_FSCAL2 : 0x0A<LF><CR>

CC1101_FSCAL1 : 0x00<LF><CR>

CC1101_FSCAL0 : 0x11<LF><CR>

CC1101_RCCTRL1 : 0x41<LF><CR>

CC1101_RCCTRL0 : 0x00<LF><CR>

CC1101_FSTEST : 0x59<LF><CR>

CC1101_PTEST : 0x7F<LF><CR>

CC1101_AGCTEST : 0x3F<LF><CR>

CC1101_TEST2 : 0x88<LF><CR>

CC1101_TEST1 : 0x31<LF><CR>

CC1101_TEST0 : 0x0B<LF><CR>

*************************************<LF><CR>

CC1101_PATABLE(0) : 0x60<LF><CR>

PARTNUM = 0x00<LF><CR>

VERSION = 0x04<LF><CR>

CC1101_MARCSTATE : 0x5F<LF><CR>

CC1101_MARCSTATE : 0x2F<LF><CR>

=====> then infinite 0x2F value.

We can see that the first read of the MARCSTATE register is 0x5F... ===> that is already strange ! the first read MARCSTATE is just after the SIDLE command !

so i expect to read 0x01 value ...? no ?

something wrong in my registers settings ?

thanks for your support

Phil

0 TA12012 over 13 years ago in reply to Philippe CHAGNY

TI__Mastermind 36395 points

Here are settings from SmartRF Studio for 38.4kbps at 915MHz

// Sync word qualifier mode = 30/32 sync word bits detected
// CRC autoflush = false
// Channel spacing = 199.951172
// Data format = Normal mode
// Data rate = 38.3835
// RX filter BW = 101.562500
// PA ramping = false
// Preamble count = 4
// Address config = No address check
// Whitening = false
// Carrier frequency = 914.999969
// Device address = 0
// TX power = 10
// Manchester enable = false
// CRC enable = true
// Deviation = 20.629883
// Modulation format = GFSK
// Base frequency = 914.999969
// Modulated = true
// Channel number = 0

static const registerSetting_t preferredSettings[]=
{
{CC1101_IOCFG0, 0x06},
{CC1101_FIFOTHR, 0x47},
{CC1101_PKTCTRL0, 0x05},
{CC1101_FSCTRL1, 0x06},
{CC1101_FREQ2, 0x23},
{CC1101_FREQ1, 0x31},
{CC1101_FREQ0, 0x3B},
{CC1101_MDMCFG4, 0xCA},
{CC1101_MDMCFG3, 0x83},
{CC1101_MDMCFG2, 0x13},
{CC1101_DEVIATN, 0x35},
{CC1101_MCSM0, 0x18},
{CC1101_FOCCFG, 0x16},
{CC1101_AGCCTRL2, 0x43},
{CC1101_WORCTRL, 0xFB},
{CC1101_FSCAL3, 0xE9},
{CC1101_FSCAL2, 0x2A},
{CC1101_FSCAL1, 0x00},
{CC1101_FSCAL0, 0x1F},
{CC1101_TEST2, 0x81},
{CC1101_TEST1, 0x35},
{CC1101_TEST0, 0x09},
};

0 Philippe CHAGNY over 13 years ago in reply to TA12012

Prodigy 120 points

now i setup your config and here it is the debug terminal report (with the same main)

*************************************<LF><CR>

CC1101_PATABLE(0) : 0x60<LF><CR>

PARTNUM = 0x00<LF><CR>

VERSION = 0x04<LF><CR>

CC1101_MARCSTATE : 0x01<LF><CR>

CC1101_MARCSTATE : 0x08<LF><CR>

CC1101_MARCSTATE : 0x13<LF><CR>

then infinite 0x13

something was wrong in my previous Main ( i was not reading the Status MARCSTATE right).

i stay in 0x13 "TXstate" ... what does it mean ?

0 TA12012 over 13 years ago in reply to Philippe CHAGNY

TI__Mastermind 36395 points

Hi,

It almost sounds like you did not successfully put data into the FIFO. Because what happens is, if there is no data in the FIFO the radio just keeps transmitting the preamble until you give it data. PS: I also forgot to have you put the radio into "Fixed packet Length mode".

change PKTCTRL0 to 0x04

{CC1101_PKTCTRL0, 0x04}

Then change PKTLEN to the number of bytes you want to transmit (this has to be below 62 bytes) here I chose 16 bytes of data.

{CC1101_PKTLEN, 0x10}

Regards
/TA

0 Philippe CHAGNY over 13 years ago in reply to TA12012

Prodigy 120 points

well i will check my "burst write" to TX_FIFO

i have change PKCTRL0 and PKTLEN as you explain, with 10 bytes to transmit. then here it is my debug trace :

*************************************<LF><CR>

CC1101_PATABLE(0) : 0x8E<LF><CR>

PARTNUM = 0x00<LF><CR>

VERSION = 0x04<LF><CR>

CC1101_MARCSTATE : 0x01<LF><CR>

MARCSTATE : 0x08<LF><CR>

MARCSTATE : 0x13<LF><CR>

MARCSTATE : 0x0D<LF><CR>

then infinite 0x0D ==> seem to be RX mode, according to the MARCSTATE description !! does it mean that i successfull fill the TX_FIFO with the 10 bytes ?

thanks for your help

phil

0 Philippe CHAGNY over 13 years ago in reply to Philippe CHAGNY

Prodigy 120 points

mmm seem much better now.

i have change the MCSM1 to 0x30.. then now

*************************************<LF><CR>

CC1101_PATABLE(0) : 0x8E<LF><CR>

PARTNUM = 0x00<LF><CR>

VERSION = 0x04<LF><CR>

CC1101_MARCSTATE : 0x01<LF><CR>

CC1101_MARCSTATE : 0x08<LF><CR>

CC1101_MARCSTATE : 0x13<LF><CR>

CC1101_MARCSTATE : 0x01<LF><CR>

the radio now go to IDLE mode after TX ==> now may i be sure than the TX side is working ?

then on the RX side, i apply same recomandation.

it seem then i stay in RX mode (MARCSTATE = 0x0D), without receive anything :(

thanks a lot

0 TA12012 over 13 years ago in reply to Philippe CHAGNY

TI__Mastermind 36395 points

Yes, you can be pretty sure the package has been sent out.

CC1101_MARCSTATE : 0x01<LF><CR> => IDLE

CC1101_MARCSTATE : 0x08<LF><CR> => Calibrate PLL

CC1101_MARCSTATE : 0x13<LF><CR> => TRANSMIT

CC1101_MARCSTATE : 0x01<LF><CR> => BACK TO IDLE

Now make a loop that keeps transmitting over and over as fast as you can.

Then setup the receiver board to enter RX (using SRX) then monitor MARCSTATE and RSSI. How much RAM do you have? If you have a lot store 1000 iterations and then go thru the results nice and slowly and you will find RSSI values changes or MARCSTATE changes.

PS: If you have the CC1101 at full power the TX and RX needs to be separated by 10-20feet or more.

Regards,
/TA

0 Philippe CHAGNY over 13 years ago in reply to TA12012

Prodigy 120 points

Hello,

well on the TX side, i decrease the PA to -10dBm, and send 10 bytes in loop, as fast as possible.

the MARCSTATE seem working as expected.

on the RX side, i apply you recomendation and run rhe RX mode by SRX command.

i store 3000 read of the MARCSTATE and print them for debug.

here it is the trace :

INIT CPU DONE<LF><CR>

Test CC1101 v1.00<LF><CR>

*************************************<LF><CR>

Dump CC1101 registers<LF><CR>

CC1101_IOCFG2 : 0x29<LF><CR>

CC1101_IOCFG1 : 0x2E<LF><CR>

CC1101_IOCFG0 : 0x06<LF><CR>

CC1101_FIFOTHR : 0x47<LF><CR>

CC1101_SYNC1 : 0xB5<LF><CR>

CC1101_SYNC0 : 0x47<LF><CR>

CC1101_PKTLEN : 0x0A<LF><CR>

CC1101_PKTCTRL1 : 0x06<LF><CR>

CC1101_PKTCTRL0 : 0x04<LF><CR>

CC1101_ADDR : 0x00<LF><CR>

CC1101_CHANNR : 0x00<LF><CR>

CC1101_FSCTRL1 : 0x06<LF><CR>

CC1101_FSCTRL0 : 0x00<LF><CR>

CC1101_FREQ2 : 0x23<LF><CR>

CC1101_FREQ1 : 0x31<LF><CR>

CC1101_FREQ0 : 0x3B<LF><CR>

CC1101_MDMCFG4 : 0xCA<LF><CR>

CC1101_MDMCFG3 : 0x83<LF><CR>

CC1101_MDMCFG2 : 0x13<LF><CR>

CC1101_MDMCFG1 : 0x22<LF><CR>

CC1101_MDMCFG0 : 0xF8<LF><CR>

CC1101_DEVIATN : 0x35<LF><CR>

CC1101_MCSM2 : 0x07<LF><CR>

CC1101_MCSM1 : 0x30<LF><CR>

CC1101_MCSM0 : 0x18<LF><CR>

CC1101_FOCCFG : 0x16<LF><CR>

CC1101_BSCFG : 0x6C<LF><CR>

CC1101_AGCCTRL2 : 0x43<LF><CR>

CC1101_AGCCTRL1 : 0x40<LF><CR>

CC1101_AGCCTRL0 : 0x91<LF><CR>

CC1101_WOREVT1 : 0x87<LF><CR>

CC1101_WOREVT0 : 0x6B<LF><CR>

CC1101_WORCTRL : 0xFB<LF><CR>

CC1101_FREND1 : 0x56<LF><CR>

CC1101_FREND0 : 0x10<LF><CR>

CC1101_FSCAL3 : 0xE9<LF><CR>

CC1101_FSCAL2 : 0x2A<LF><CR>

CC1101_FSCAL1 : 0x00<LF><CR>

CC1101_FSCAL0 : 0x1F<LF><CR>

CC1101_RCCTRL1 : 0x41<LF><CR>

CC1101_RCCTRL0 : 0x00<LF><CR>

CC1101_FSTEST : 0x59<LF><CR>

CC1101_PTEST : 0x7F<LF><CR>

CC1101_AGCTEST : 0x3F<LF><CR>

CC1101_TEST2 : 0x81<LF><CR>

CC1101_TEST1 : 0x35<LF><CR>

CC1101_TEST0 : 0x09<LF><CR>

*************************************<LF><CR>

PARTNUM = 0x00<LF><CR>

VERSION = 0x04<LF><CR>

CC1101_MARCSTATE = 0x01<LF><CR>

CC1101_MARCSTATE = 0x07<LF><CR>

CC1101_MARCSTATE : 0x0D<LF><CR>

then infinite 0x0D .. it seem that i receive nothing :(

please, note that i don't capture the step 0x8 0x9 0xA and "jump direcly" to 0xD .. maybe my CPU is not speed enough ???

(this is a PIC @25MHz, with SPI at max speed)

the configuration registers is the same as for the TX side .. please do you see something wrong ?

thanks, regards

phil

0 TA12012 over 13 years ago in reply to Philippe CHAGNY

TI__Mastermind 36395 points

I found two more issues:

For some reason you have changed the Sync words, this should still work however I have not tested. We recommend using our sync word or change it to a different "Gold Code".

But I think the reason it is not finding anything is that you have enabled Address checking and honestly I have never used. Just disable it by changing PKTCTRL1 to 0x04.

Regards,
/TA

CC1101_SYNC1 : 0xD3

CC1101_SYNC0 : 0x91

CC1101_PKTCTRL1 : 0x04

0 Philippe CHAGNY over 13 years ago in reply to TA12012

Prodigy 120 points

yes i'm sorry, i had some bad values in the "default_config". now i modify as you suggest :

INIT CPU DONE<LF><CR>

Test CC1101 v1.00<LF><CR>

*************************************<LF><CR>

Dump CC1101 registers<LF><CR>

CC1101_IOCFG2 : 0x29<LF><CR>

CC1101_IOCFG1 : 0x2E<LF><CR>

CC1101_IOCFG0 : 0x06<LF><CR>

CC1101_FIFOTHR : 0x47<LF><CR>

CC1101_SYNC1 : 0xD3<LF><CR>

CC1101_SYNC0 : 0x91<LF><CR>

CC1101_PKTLEN : 0x0A<LF><CR>

CC1101_PKTCTRL1 : 0x04<LF><CR>

CC1101_PKTCTRL0 : 0x04<LF><CR>

CC1101_ADDR : 0x00<LF><CR>

CC1101_CHANNR : 0x00<LF><CR>

CC1101_FSCTRL1 : 0x06<LF><CR>

CC1101_FSCTRL0 : 0x00<LF><CR>

CC1101_FREQ2 : 0x23<LF><CR>

CC1101_FREQ1 : 0x31<LF><CR>

CC1101_FREQ0 : 0x3B<LF><CR>

CC1101_MDMCFG4 : 0xCA<LF><CR>

CC1101_MDMCFG3 : 0x83<LF><CR>

CC1101_MDMCFG2 : 0x13<LF><CR>

CC1101_MDMCFG1 : 0x22<LF><CR>

CC1101_MDMCFG0 : 0xF8<LF><CR>

CC1101_DEVIATN : 0x35<LF><CR>

CC1101_MCSM2 : 0x07<LF><CR>

CC1101_MCSM1 : 0x30<LF><CR>

CC1101_MCSM0 : 0x18<LF><CR>

CC1101_FOCCFG : 0x16<LF><CR>

CC1101_BSCFG : 0x6C<LF><CR>

CC1101_AGCCTRL2 : 0x43<LF><CR>

CC1101_AGCCTRL1 : 0x40<LF><CR>

CC1101_AGCCTRL0 : 0x91<LF><CR>

CC1101_WOREVT1 : 0x87<LF><CR>

CC1101_WOREVT0 : 0x6B<LF><CR>

CC1101_WORCTRL : 0xF8<LF><CR>

CC1101_FREND1 : 0x56<LF><CR>

CC1101_FREND0 : 0x10<LF><CR>

CC1101_FSCAL3 : 0xE9<LF><CR>

CC1101_FSCAL2 : 0x2A<LF><CR>

CC1101_FSCAL1 : 0x00<LF><CR>

CC1101_FSCAL0 : 0x1F<LF><CR>

CC1101_RCCTRL1 : 0x41<LF><CR>

CC1101_RCCTRL0 : 0x00<LF><CR>

CC1101_FSTEST : 0x59<LF><CR>

CC1101_PTEST : 0x7F<LF><CR>

CC1101_AGCTEST : 0x3F<LF><CR>

CC1101_TEST2 : 0x81<LF><CR>

CC1101_TEST1 : 0x35<LF><CR>

CC1101_TEST0 : 0x09<LF><CR>

*************************************<LF><CR>

PARTNUM = 0x00<LF><CR>

VERSION = 0x04<LF><CR>

CC1101_MARCSTATE = 0x01<LF><CR>

CC1101_MARCSTATE = 0x07<LF><CR>

CC1101_MARCSTATE : 0x0D<LF><CR>

and again i stay in 0x0D mode ==> receive nothing :(

i check the GDO0 line, it's always '0' ( after config done). according to Table 41, i don't receive SYNC word or i discard all packets..

but Address is not checked now (PKCTRL0 = PKCTRL1 = 0x04) and LENGHT is fixed (PKTLEN = 0x0A)

( i check GDO0 on the TX side, and toggle as expected. the TX side seem working again !)

do you notice something wrong again ?

thanks for your help and patience !, regards

Phil

0 Philippe CHAGNY over 13 years ago in reply to Philippe CHAGNY

Prodigy 120 points

well, many thanks for your guidance. i have a working system now.. not perfectly but i think i can manage it rigt now.

best regards

phil

0 or sam over 13 years ago in reply to Philippe CHAGNY

Expert 2020 points

I think I have the same problem as you.

How did you fixed it? what was wrong the GDO0 is always in my module to.

Thanks in advanced.

0 Philippe CHAGNY over 13 years ago in reply to or sam

Prodigy 120 points

use the MARCSTATE register to debug the state machine ..

usefull

most of my problems was in the bad registers configuration .. lot of information to read . but that's the way !

regards

0 or sam over 13 years ago in reply to Philippe CHAGNY

Expert 2020 points

as much as trying I couldn't find what is wrong with my setting.

did you had a register that fixed your problem that the SO that was always on low? can you upload your setting to see what could be wrong in my?

thanks in advenced.

0 Philippe CHAGNY over 13 years ago in reply to or sam

Prodigy 120 points

hi had no problems with the SPI bus ..

what is your problem exactly ?

0 or sam over 13 years ago in reply to Philippe CHAGNY

Expert 2020 points

you wrote:

"i check the GDO0 line, it's always '0' ( after config done). according to Table 41, i don't receive SYNC word or i discard all packets.."

this is exactly what I see.

constant zero on gdo0.

thanks,

0 Philippe CHAGNY over 13 years ago in reply to or sam

Prodigy 120 points

check the MCSM1, PKTCTRL0, PKTCTRL1 and IOCFG registers

'//
'Here are settings from SmartRF Studio for 38.4kbps at 915MHz
'
'// Sync word qualifier mode = 30/32 sync word bits detected
'// CRC autoflush = false
'// Channel spacing = 199.951172
'// Data format = Normal mode
'// Data rate = 38.3835
'// RX filter BW = 101.562500
'// PA ramping = false
'// Preamble count = 4
'// Address config = No address check
'// Whitening = false
'// Carrier frequency = 914.999969
'// Device address = 0
'// TX power = 10
'// Manchester enable = false
'// CRC enable = true
'// Deviation = 20.629883
'// Modulation format = GFSK
'// Base frequency = 914.999969
'// Modulated = true
'// Channel number = 0'//
CC1101_WriteReg(CC1101_IOCFG0,   0x06) 'GDO0 Output Pin Configuration
CC1101_WriteReg(CC1101_FIFOTHR, 0x47) 'RX FIFO and TX FIFO Thresholds
CC1101_WriteReg(CC1101_PKTCTRL1, 0x04) 'Packet automation control.
CC1101_WriteReg(CC1101_PKTCTRL0, 0x04) 'Packet Automation Control ----> fixed packet lenght
CC1101_WriteReg(CC1101_PKTLEN,   0x0A) 'packet lenght ! 10 bytes
CC1101_WriteReg(CC1101_SYNC1,    0xD3)
CC1101_WriteReg(CC1101_SYNC0,    0x91)
CC1101_WriteReg(CC1101_FSCTRL1, 0x06) 'Frequency Synthesizer Control
CC1101_WriteReg(CC1101_FREQ2,    0x23) 'Frequency Control Word, High Byte
CC1101_WriteReg(CC1101_FREQ1,    0x31) 'Frequency Control Word, Middle Byte
CC1101_WriteReg(CC1101_FREQ0,    0x3B) 'Frequency Control Word, Low Byte
CC1101_WriteReg(CC1101_MDMCFG4, 0xCA) 'Modem Configuration
CC1101_WriteReg(CC1101_MDMCFG3, 0x83) 'Modem Configuration
CC1101_WriteReg(CC1101_MDMCFG2, 0x13) 'Modem Configuration
CC1101_WriteReg(CC1101_DEVIATN, 0x35) 'Modem Deviation Setting
CC1101_WriteReg(CC1101_MCSM1,    0x30) 'Main Radio Control State Machine Configuration
CC1101_WriteReg(CC1101_MCSM0,    0x18) 'Main Radio Control State Machine Configuration
CC1101_WriteReg(CC1101_FOCCFG,   0x16) 'Frequency Offset Compensation Configuration
CC1101_WriteReg(CC1101_AGCCTRL2, 0x43) '
CC1101_WriteReg(CC1101_FSCAL3,   0xE9) 'Frequency Synthesizer Calibration
CC1101_WriteReg(CC1101_FSCAL2,   0x2A) 'Frequency Synthesizer Calibration
CC1101_WriteReg(CC1101_FSCAL1,   0x00) 'Frequency Synthesizer Calibration
CC1101_WriteReg(CC1101_FSCAL0,   0x1F) 'Frequency Synthesizer Calibration
CC1101_WriteReg(CC1101_TEST2,    0x81) 'Various Test Settings
CC1101_WriteReg(CC1101_TEST1,    0x35) 'Various Test Settings
CC1101_WriteReg(CC1101_TEST0,    0x09) 'Various Test Settings

0 or sam over 13 years ago in reply to Philippe CHAGNY

Expert 2020 points

Phil Hi

thanks for your help.

Finally I found what was wrong....

I havent flushed my RX fifo and this cause the gdo0 to be low all the time.

thank you very much for your help.

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