Maybe this is too much info below. I'm having Rx problems related to using LPM's. Maybe someone can explain the relationship here, but then maybe I'm posting on the wrong category? (Side note: Wouldn't mind a CC430 category. Honestly, I never know if I should post on the MCP430, Controllers, or RF categories.) Anyway, just frustrated and sharing my problem again on the CC430 implementation. Any suggestions or help here?
Thanks,
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First, I'm fresh out of dongle connectors (from the Chronos kit), so I soldered a dongle onto our board for ease of development. Seems it can only run now with power connected to the dongle and will not run with just power to my board. This leads me to believe the CC430 could be behaving differently to possibly cause other runtime problems... such as this (swag)???
The symptom is that when we loop the main using LPM0 (or LPM3) I don't miss any RF Rx packets, however the system hangs when we try to write out the ports (I2C or MIDI). Now, remove the LPM and just set the GIE and we miss about every other packet and more at times, even at close range.
So, it's probably not the dongle issue (but never know), so thinking that by the time we receive a packet then quickly use the port ISRs to transmit the data out the serial ports, we're having power problems and it hangs. Here's the main loop and port config. Maybe this has to do with the MCLK being off in LPM? So maybe we just need a delay for the clock before writing to the ports. But what's with the missing packets when LPM is not used? We know it happens when we write the ports because we reduced it down to just that operation, and we know it hangs because we set the LED to constantly flash when running.
Thanks for any clues here! By the way, it's now public what I'm doing and we're pretty close to a product kickoff. Check out "Cleanstage LLC" on Facebook if you're curious about SoulPedal(TM), Patent Pending.
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Main...
while( true ) {
// __bis_SR_register(LPM0_bits + GIE ); // Doesn't miss data, but locks
__bis_SR_register( GIE ); // Misses Data, doesn't lock up.
if (radio->packetReceived) { // set in the Rx ISR
radio->packetReceived = 0;
if ( ((enum _packet_type)radio->rxBuffer[0] & PKTHDR_MASK) == ACCEL_DATA_TYPE) { // If the packet header is of type Accelerometer data...
radio->linkStatus = STATUS_LINK_ACTIVE;
radio->linkStatusInactiveCount = 0;
processAccelData (0); // this sends the data out the ports
}
}
radio->receiveOff();
radio->receiveOn();
__delay_cycles(5000);
if (++potSampleCount > 5) {
potSampleCount = 0;
pot->readPotValues(); // read the ADC on 3 channels
}
}
Port Setup....
// MIDI Serial port
// UCSCTL6 &= ~XT2OFF; // Enable XT2 (26MHz) Don't need because Radio should be ready
UCSCTL4 |= SELS__XT2CLK; // SMCLK=XT2 (26Mhz Clock)
__delay_cycles(50000); // probably not needed
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK to UCA0
UCSCTL5 |= DIVS_1; // /2
UCA0BR0 = 160; // 64/2
UCA0BR1 = 1; //
UCA0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
// *** I2C code ***
P1MAP3 = PM_UCB0SDA; // Map UCB0SDA output to P1.4
P1MAP2 = PM_UCB0SCL; // Map UCB0SCL output to P1.2
P1SEL |= BIT2 + BIT3; // Select P1.2 & P1.3 to I2C function
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x2C; // Slave is 00b, Total addr is 58 plus Write bit
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCTXIE + UCNACKIE; // Enable TX interrupt, monitor for NACK (No Acknowledge)
// *** End I2C code ***
PMAPPWD = 0;