Other Parts Discussed in Thread: CC1200
When using Standard FIFO Access to read the CC1200's RX FIFO, there appears to be some kind of glitch that occurs sometimes when the RX packet ends during the FIFO read operation. This glitch does not occur all the time: Only ~2% of the time in my application, so the time jitter on my read operation is randomly hitting the critical window for the chip's internal race condition. On looking at the received data when this occurs, the received bytes appear to be shifted by 1 bit position, as if one extra spurious SPI clock had occurred. Because of this error, after reading the NUM_RXBYTES register to determine the number of bytes in the RX FIFO and then trying to read those bytes from the RX FIFO, an RX FIFO Underflow errors occurs. This is a serious issue in a time-critical application such as mine, since clearing the FIFO error requires going back to IDLE mode, and trying to avoid the error requires suppressing FIFO read operations in proximity to the anticipated end of packet. Is this a known problem or a new problem? While it is always possible that this is a firmware issue, I have looked and not seen any SPI clock glitches on my signals that could be causing this problem.
