• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 16 subscribers
  • Views 236 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC430

Jaden Ghylin102047
Expert 1140 points
Other Parts Discussed in Thread: CC430F6137, TEST2

I have been trying to get the CC430 working with a legacy wireless system and am having some difficulty. I am running the CC430 as a receiver, asynchronous mode. The wireless packet being sent over uses different length pulses to generate symbols. (See attached file)

 

Each of the symbols is a symmetric pulse, and the duration between the rising edges determines which symbol it is.

 

Symbol |  Width (uS)

00       | 72

01       | 98

10       | 126

11       | 156

 

My issue is that I am unable to receive a symmetric pulse. I can see the first part of the preamble, but after that the there are random transitions everywhere. My question is can the CC430 support this transmission scheme and my settings are just wrong? Or will this legacy system not work with a 430?  My understanding of what I am seeing is  that the bit timing generator is still trying to run even though I set it to async mode.

 

RF Settings

27MHz crystal

433.92MHZ center frequency

25kHz deviation

2-FSK

 

If I remember correctly, my buad was set to 28kHz, and RX bandwidth set to 150kHz 

 

Here are my settings (generated with RF Studio). 

 

#define SMARTRF_RADIO_CC430F6137

#define SMARTRF_SETTING_IOCFG2        0x0D

#define SMARTRF_SETTING_IOCFG1        0x2E

#define SMARTRF_SETTING_IOCFG0        0x0D

#define SMARTRF_SETTING_FIFOTHR       0x07

#define SMARTRF_SETTING_SYNC1         0xD3

#define SMARTRF_SETTING_SYNC0         0x91

#define SMARTRF_SETTING_PKTLEN        0xFF

#define SMARTRF_SETTING_PKTCTRL1      0x04

#define SMARTRF_SETTING_PKTCTRL0      0x32

#define SMARTRF_SETTING_ADDR          0x00

#define SMARTRF_SETTING_CHANNR        0x00

#define SMARTRF_SETTING_FSCTRL1       0x0C

#define SMARTRF_SETTING_FSCTRL0       0x00

#define SMARTRF_SETTING_FREQ2         0x10

#define SMARTRF_SETTING_FREQ1         0x12

#define SMARTRF_SETTING_FREQ0         0x34

#define SMARTRF_SETTING_MDMCFG4       0x99

#define SMARTRF_SETTING_MDMCFG3       0x4A

#define SMARTRF_SETTING_MDMCFG2       0x00

#define SMARTRF_SETTING_MDMCFG1       0x22

#define SMARTRF_SETTING_MDMCFG0       0xE5

#define SMARTRF_SETTING_DEVIATN       0x37

#define SMARTRF_SETTING_MCSM2         0x07

#define SMARTRF_SETTING_MCSM1         0x30

#define SMARTRF_SETTING_MCSM0         0x10

#define SMARTRF_SETTING_FOCCFG        0x1D

#define SMARTRF_SETTING_BSCFG         0x1C

#define SMARTRF_SETTING_AGCCTRL2      0xC7

#define SMARTRF_SETTING_AGCCTRL1      0x00

#define SMARTRF_SETTING_AGCCTRL0      0xB0

#define SMARTRF_SETTING_WOREVT1       0x87

#define SMARTRF_SETTING_WOREVT0       0x6B

#define SMARTRF_SETTING_WORCTRL       0xFB

#define SMARTRF_SETTING_FREND1        0xB6

#define SMARTRF_SETTING_FREND0        0x10

#define SMARTRF_SETTING_FSCAL3        0xE9

#define SMARTRF_SETTING_FSCAL2        0x2A

#define SMARTRF_SETTING_FSCAL1        0x00

#define SMARTRF_SETTING_FSCAL0        0x1F

#define SMARTRF_SETTING_FSTEST        0x59

#define SMARTRF_SETTING_PTEST         0x7F

#define SMARTRF_SETTING_AGCTEST       0x3F

#define SMARTRF_SETTING_TEST2         0x88

#define SMARTRF_SETTING_TEST1         0x31

#define SMARTRF_SETTING_TEST0         0x09

#define SMARTRF_SETTING_PARTNUM       0x00

#define SMARTRF_SETTING_VERSION       0x06

#define SMARTRF_SETTING_FREQEST       0x00

#define SMARTRF_SETTING_LQI           0x00

#define SMARTRF_SETTING_RSSI          0x80

#define SMARTRF_SETTING_MARCSTATE     0x00

#define SMARTRF_SETTING_WORTIME1      0x00

#define SMARTRF_SETTING_WORTIME0      0x00

#define SMARTRF_SETTING_PKTSTATUS     0x00

#define SMARTRF_SETTING_VCO_VC_DAC    0x94

#define SMARTRF_SETTING_TXBYTES       0x00

#define SMARTRF_SETTING_RXBYTES       0x00

#define SMARTRF_SETTING_RF1AIFCTL0    0x00

#define SMARTRF_SETTING_RF1AIFCTL1    0x00

#define SMARTRF_SETTING_RF1AIFCTL2    0x00

#define SMARTRF_SETTING_RF1AIFERR     0x00

#define SMARTRF_SETTING_RF1AIFERRV    0x00

#define SMARTRF_SETTING_RF1AIFIV      0x00

#define SMARTRF_SETTING_RF1AINSTRW    0x00

#define SMARTRF_SETTING_RF1AINSTR1W   0x00

#define SMARTRF_SETTING_RF1AINSTR2W   0x00

#define SMARTRF_SETTING_RF1ADINW      0x00

#define SMARTRF_SETTING_RF1ASTAT0W    0x00

#define SMARTRF_SETTING_RF1ASTAT1W    0x00

#define SMARTRF_SETTING_RF1ASTAT2W    0x00

#define SMARTRF_SETTING_RF1ADOUT0W    0x00

#define SMARTRF_SETTING_RF1ADOUT1W    0x00

#define SMARTRF_SETTING_RF1ADOUT2W    0x00

#define SMARTRF_SETTING_RF1AIN        0x00

#define SMARTRF_SETTING_RF1AIFG       0x00

#define SMARTRF_SETTING_RF1AIES       0x00

#define SMARTRF_SETTING_RF1AIE        0x00

#define SMARTRF_SETTING_RF1AIV        0x00

#define SMARTRF_SETTING_RF1ARXFIFO    0x00

#define SMARTRF_SETTING_RF1ATXFIFO    0x00

  • 0
    TI__Mastermind 39860 points

    The asynchronous serial mode gives access to raw demodulator data without any data decision. The data stream is a time-discrete using 8 samples per bit. If you program 17 kbps, each bit is 59 us. The "jitter" can then be +/-7.35 us (59/8). In asynchronous serial mode you can see the un-synchronous data has this jitter or even spikes due to noise because no bit desicion is done in the chip.

    In your case the the symbols have different width so one thought is to program the CC430 to a high data to increase the resolution. Using 100 kbps (say) instead of 17 kbps will give less jitter due to higher samplings rate. Try changing MDMCFG4 to 0x9B and MDMCFG3 to 0xE5.