Dear All,
I am having some difficulites understanding the cc2591 design files. No matter what I try, I cannot open the files for editing, only viewing via the latest CADSTAR 11 viewer. How could I edit those, if we do not own a Mentor Graphics editing software? I have Autocad, Protel, Orcad access, but not really worked with the Cadstar or Mentor Graphics software.
Best wishes and a Happy New Year 2010!
Ghasem
The antenna is on the top layer. I opened the converter file and saw the same thing. It looks like the polygon pours are lost in the translation.
The following is the file in Altium (Summer 2009) where it looks like all of the layers are intact including split polygons. Can you use Altium files or a full set of Gerbers? By DXP do you mean Altium?
Here are the 4 planes. Other than ground vias there are no QFN pads on layers 2-4
A common 4 layer board is like this:
1 ---Top signal Layer with copper pour connnect to ground-----
2 ------------------------ Ground plane ---------------------------------
3 ----------------------- +3Vdd Plane -----------------------------------
4 ------------------------ Ground Plane ---------------------------------
All vias go through all layers top to bottom. (Yes, it possible to have "blind" vias that go between layer pairs but it costs a lot more.) The nice thing about 4 layers with a power and ground plane is if you need power or ground you just pop in a via and you are connected. You do not have to route traces for power or ground. They are always there by adding a via. The BIG advantage is the ground plane is continuous, without breaks, because it does not have lines. A continuous ground plane is important at 2.4GHz. If you look at a simple Ti design like a CC2430EM you will see the ground plane on the bottom layer under the RF matching section does not have a single break or line. With more complex designs this becomes nearly impossible with 2 layers.
If you look at the photo where I zoomed in on the Vdd lines for the CC2591 notice how the Vdd comes from the via, goes to the bypass cap which is grounded with a via, and then to the CC2591. The lines are short, the ground pour on the top, layer 2 and the bottom are not broken by a Vdd trace, and the person doing the layout didn’t have to figure how to route the power all over the board. There is little worry of coupling between devices due to a long Vdd line connecting them which could cause feedback and oscillations. When you route a Vdd line and add a via it automatically connects to the Vdd plane.
The power and ground plane do not have signal traces on them. All signals are on the top and bottom.
I will try to up load the Altium files. Which version of Altium do you have?
The files are from Altium Summer 2009 SP3 (ver 9.1.0.18363 ) which is the most current and is up todate.
To answer some of your questions:
The layer order is Top(Layer 1), Ground(2), Power(3), and Bottom(4). The reason is the RF transmission lines are of a certain impedance. Impedance is controlled by the dielectric properties of the PCB material, the width of the line, AND the thickness of the PCB material between the line and the plane below it. If the power plane is directly under the RF lines on layer 1 then the power plane becomes the RF ground plane which, while possible, is difficult because the Ti chips use the same “ground” for dc and RF.
All of the vias go from top to bottom. If the via is on net VCC and the power plane is also net VCC the via will automatically attach to the VCC plane2 (3). It will automatically have a clearance gap where it goes through the ground plane(2) and also on the bottom(4) so it does not connect to the copper pour on the bottom which is connected to net ground.
Look carefully at the picture from the Altium Layer Stack Manager to see this better. My power plane labeled VCC is only connected to +3.3Vdc output of the voltage regulator. You can use a layer instead of a plane where it is possible to use polygons to define different areas connected to different nets (ex.: Net Vdd3.3V, Net Vdd5V,)
In PCB design (OrCad, Eagle, Altium, etc) the schematic is King. The schematic defines the interconnects, the foot prints are associated with the symbols here. The net list will be output from the schematic editor. Once the schematic is finished you are nearly done. Once you convert it to layout you will see all of the footprints with fine lines (so called "air wires") between them so you know how to route lines between them. It will not let you connect a line to the wrong pin. If you miss a connection the design rule checker with catch it. If you click a net on the schematic it will light up on the layout. If you click a net on the layout everything on that net on the layout will light up as will the same net on the schematic. (This is where two screens are real nice but one screen with both the layout and schematic works too). This all works provided the schematic is complete, the schematic symbols are accurate, and the foot print pins match the symbol's pins.
Symbols and Footprints: The forums are full of people looking for symbols and foot prints. I do not understand this. They are quick and easy to make and every time I use one from an open library I seem to have a problem with it.
Step 1 is to pick a PCB CAD tool and complete the schematic including symbols and foot prints.
Let me know if you need help.
You have a earlier version of Altium so everything is not the same as mine in term of menus or feature but the basic functions are still if you can find them. I can tell you how to do it in Altium 9.1 then we will have to figure it out.
A good tool for capturing screen shots is at Screenshot32.com It is free, once set up you press "Print Screen", drag a box around what you want, right click, and it saves a .jpg to a file.
Adding Planes under the design tab I have "Layer Stack Manager". I'm sure you have something like this.
On a blank part of the lay out area right click, select Option, then select Edit Nets... Here under Net Class add GND, set the annular ring size, hole size, and line width. (ex 40mils, 20mils, 10mils) Once the nets are established you can go to the next step (If you have a schematic all of the nets would already be here). I'm trying to find a way to add all of the nets to a table to save some work.
In stack manager I click the top layer, then click Add Plane. Once it is added I double click it add set the Net name to GND.
Still In stack manager I click the bottom layer, then click Add Plane. Once it is added I double click it add and set the Net name to VCC or what ever you are using. If you want more than one plane on this layer click Add Layer. Later you can select this layer a draw a polygon for each plane and attach each one to a different Net (eg VCC33 and VCC5)
To add the vias there are 2 ways to go. Select place, via, and put the via where you want it. Select the via, right click it, and it properties add the name of the Net it is attached to. The second way is to route a line to where you want the via, push the + key and a via will appear, click once to fix it in place. You can push the L key to change the layer you are routing on.
Lines that are ready routed can be named by selecting them, right clicking, properties, and select the net name.
Here is what I see. Cctrl H works nice, I didn't know about it before your posting. On layer 2 you can see the 4 vias connected to Layer 2 (Net GND), on layer 3 there is the clearance and no connection for the GND vias but you can see pin 9 of the 10 pin header is connected to VCC and had clearance on Layer 2 (GND). I just put the ten pin connector down, right click on pin 9 and selected VCC for the net. The software did the rest.
If a pin that is passing through the board is not on net VCC or GND it will not connect. There is nothing you have to do. Even when you add copper pour to the top and bottom and attach them to GND only thru hole pins on Net GND will be attached to tese pour as shown below. Note the relief around VCC and pin 10. It is automatic.
I did the same thing by starting with a new project. I defined a Net call VCC, I added a Plane for Net VCC and then added 3 vias adding only 1 of them to Net VCC. I routed the 3 vias at which point they all became named VCC. I added via 4 and used properties to define its Net as VCC.
After selecting ctrl H and clicking the end of the free line everthing, including the unatached via was high lighted. I might think it was a software version differece but you saw it work with a previous file. Maybe it only works in the older vesion if there is a Net list from schematic?
