• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 17 subscribers
  • Views 582 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

cc1100 based transceiver comm link -- receiving packets in variable length mode

fred collins
Prodigy 20 points
Other Parts Discussed in Thread: CC1100, CC1101, CC110L

I have two cc1100 transceiver boards which are separated by over 6 ft (to prevent receiver saturation). They are

identically configured using the SmartRFV7 easy setup link to communicate in the 900MHz ISM band at 250kbs,

MSK modulation, 542kHz receiver BW, 4byte preamble, 30/32 bit sync bytes (0xd3,0x91), CRC enabled, and

append status bytes enabled. Both boards are identically configured with the exception of GPIO functions.

The transmitter's GPIO2 is config. as 0x06 (high on sync sent and low on end of packet).  The GPIO2 line looks

correct (high for the expected transmission time of  a 20 byte payload (19 data bytes + 1 length byte) and a

transmission rate of 250kbs (not including the 8 preamble/sync bytes).

On the receiver side, GPIO2 is config. as either 0x06 (high on sync detected and low on end of packet) or 0x07

(high on good CRC detected).  Neither line goes high when sending packets from the transmitter.  If the GPIO2


 function is changed to 0x0e (carrier sense -- high if RSSI is above threshold) it goes high during the entire packet


 transmission from the beg. of the preamble to the last status byte as measured against the transmitter pulse. 

Further, if the GPIO2 function is changed to 0x16 (RX_HARD DATA[1]), one can see the recovered data (with

random noise on either side of the packet transmission pulse) that corresponds exactly  to the payload data

(visually superimposing a clock train to latch the bits on the data line). 

I've tried varying the frequency offset register (FSCTRL0) on one board to account for minor variances in the

reovery and generation clocks without success. I have also varied the CS_Mode between 00 (no carrier sensing

used) to 0x11 (RSSI below threshold) -- also to no avail. 

On a side note: the SmartRF recommended setting for reg. TEST0 of 0x09, disables the VCO calib. selection

stage and will hangup the autocalib. routine unless it's changed back to the reset default of 0x0b.

Is there something obvious that I'm missing?      

                                                                                                  Regards,

                                                                                                       Fred

  • 0
    TI__Genius 12735 points

    Hi Fred

    If you try one of the other settings from SmartRF Studio (e.g 38.4 kbps setting) are you able to get a link then?

  • 0 in reply to Martin B
    Prodigy 20 points

    The link works at 38kbs (pkt complete pulse & data verified). I bumped up the data rate until the link failed which

    was at 160.278kbs (MDMCFG3 = 0x93). The receiver BW was left at 541KHz since sensitivity isn't an issue at this

    point. The IF freq. was decreased to 228.5KHZ (FSCTR1=0x09) and this pushed the data rate upto 165.039kbs

    (MDMCFG3 = 0xa0).  Adding a couple of states (0x02) to the Freq. ofs reg -- FSCTRL0 -- yielded 170kbs.  At 180

    kbs the GPIO fct 0x06 is high during the entire xmssn pulse. Fct 0x07 is high for only 10% of the packets meaning

    90% fail the crc ck.  Unfortunately, the application requires all of the 250k data bandwidth.

     Would changing out the c1100 chips for c1101s' with a more robust PLL design offer any significant advantage?

      Also, is there an algorithm for calculating PA register values of output power for any specified dbm? 

      In other words, what register values vary the output power from Pmin to Pmax with the smallest

     step change or max. resolution for say the 900MHz ISM band.

                           Regards,

                               Fred

  • 0 in reply to fred collins
    TI__Mastermind 18780 points

    hi,

    What hw are you using? I did  a quick test with two EMs and smartRF studio, and they worked fine with the 250 kbps settings? They did not work when setting test0 to 0x0B though, and this is to be expected. The cc110x has two VCOs and setting this bit will make the device choose the wrong VCO and you will get the wrong RF frequency. For complete PA tables see DN012 http://www.ti.com/lit/an/swra150a/swra150a.pdf note that these numbers are taken with multilayer inductors, using wirewound inductors will give you 1-2 dB more output power. For new designs, I would recommend using the CC1101 or CC110L, the main upgrades are described in dn009 http://www.ti.com/lit/an/swra145a/swra145a.pdf.