• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 16 subscribers
  • Views 328 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Transparent Mode accuracy drift

George Pikoulis
Prodigy 120 points
Other Parts Discussed in Thread: CC1101

Consider the following setup:

 

MCU sends transparent data to CC1101 (EM) GPO0  and analog receiver captures the data. Logic analyzer probes are placed on GPO0 line and analog receiver output line.

The analog receiver is tested and proven accurate and CC1101 setting are copied from Smart RF studio.

The MCU sends a simple square signal for testing purposes, 1600 usec period, 50% duty cycle (800usec low and high logic).

I am aware that Smart RF studio is not optimized to generate settings for transparent mode (I have already read the application notes concerning transparent mode registers), but do you have any ideas on what could cause a variable delay on logic transition?

The high to low logic transition lags for about 100usec at the begining, the lag drops to zero after about 80msec in TX and starts to lead at about 40usec after 60msec in TX.

The interesting part in this scenario is that the period is always 1600usec, the duty cycle is the only variable.

I have tested this scenario with baud rates from 1.2k up to 100k, the results vary but the lag and lead are always there.

Any insight on the subject?

  • 0
    TI__Mastermind 39860 points

    If my understanding is correct you program CC1101 into asynchronous serial mode. The asynchronous serial mode gives access to raw demodulator data without any data decision. The data stream is a time-discrete using 8 samples per bit.  If you program 1.2  kBaud, each bit is 833 us. The "jitter" can then be +/-104 us (26/8).  In asynchronous serial mode mode you can see the un-synchronous data has this jitter or even spikes due to noise because no bit desicion is done in the chip.

  • 0 in reply to Sverre
    Prodigy 120 points

    Sverre thank you for your time.

    You are correct, I am talking about asynchronous transparent mode. Your answer made me understand the nature of the problem.

    As a footnote, do you believe that synchronous transparent mode would be a more resistant to jitter?

  • 0 in reply to George Pikoulis
    TI__Mastermind 39860 points

    Serial synchronous mode is a better solution. This mode has the advantage that the data clock is available and that bit synchronisation and data decision is done on-chip. (In serial asynchronous mode, you need to make sure that the MCU does proper oversampling and that it can handle the jitter the RF communication introduces).