DMA channel 2 setup on CC1110

Marcelo Peres

I have a doubt about how to configure DMA channels 2,3 and 4 on CC1110.

I intend to use all the 5 DMA channels for different functions (tx radio, rx radio, aes up, aes down and flash) but I can't understand at all how to set the channels above the second one (channel 1).

I haven't found any information about how to do so on internet, and the datasheet is very complicated to understand.
It says: "DMA1CFGH:DMA1CFGL gives the start address for DMA channel 1 configuration data structure followed by channel 2 - 4 configuration data structures." And then: "This means that the DMA controller expects the DMA configuration data structures for DMA channels 1 - 4 to lie in a contiguous area in memory, starting at the address held in DMA1CFGH:DMA1CFGL and consisting of 32 bytes."

The problem is that when I look it up how is the SRF register on the unified memory space, I can see that DMA1CFGL= 0xDFD2, DMA1CFGH = 0xDFD3 and DMA0CFGL = 0xDFD4.
So, how can I configure other DMA channels other than channel 1 and 2, which are already working very well ? What is the adress which should I put the DMA channel 2 (and so on) configuration ?

Please someone help me with some code example or at least some information !!

Thanks very much,

Marcelo Peres.

over 11 years ago

0 Siri over 11 years ago

TI__Guru* 85791 points

Hi Marcelo

DMA1CFGL and DMA1CFGH are register located at 0xD2 and 0xD3 (SFR). In your code you allocate space to a data structure in memory holding the DMA configuration for channel1. DMA1CFGL and DMA1CFGH are then given the address of the first byte in that structure.

In our code examples this is done like this:

__xdata DMA_DESC dmaConfigTX; // Struct for the DMA configuration

SET_WORD(DMA1CFGH, DMA1CFGL, &dmaConfigTX); // DMA1CFGL and DMA1CFGH hold the address of dmaConfigTX

The DMA structure consists of 8 bytes. This means that you in SW must make sure that the structure for the DMA configuration used to configure channel 2 is located with an offset of 8 bytes from the address that is written to DMA1CFGL and DMA1CFGH (the address of dmaConfigTX).

The address of the config. Struct. for channel 2 (and 3 and 4) does not have to be written to any registers.

Siri

0 Marcelo Peres over 11 years ago in reply to Siri

Prodigy 35 points

Hi Siri,

Thanks for your reply, but I'm still missing some detail because my code isn't working yet.

Here is the thing, I did the same as the DMA example from TI for channels 0 and 1, with the struct and everything. This is working very well.

What I still don't get is how the SFR register (just 1 byte according the datasheet) in 8051 memory space and Hardware SFR Registers in Physical Memory (according Xdata Mapped SFRs in "ioCC1110.h") can hold 8 bytes if it are mapped as 1 byte register (e.g. 0xD2 in 8051 memory space, 0xDFD2 in physical memory)?

If I didn't get wrong your reply, should I put the DMA struct config for channel 2 addressing like that?
#define DMA2CFGH XREG( 0xDFDB )
#define DMA2CFGL XREG( 0xDFDA )
Aren't these addresses belonging to T1CC0L and T2CC0H ?

Please help me with some code example of how I can do the offset of 8 bytes that you are telling me about, in the DMA channel 2 (and 3 and 4) setup. If you could help with a example of how to do that I'll be very thankful!

Best Regards,

Marcelo Peres.

0 Siri over 11 years ago in reply to Marcelo Peres

TI__Guru* 85791 points

The two eight bits addresses (DMA1CFGL and DMA1CFGH) points to the first byte in the 8 bytes long struct. Assume that you are going to use channel 1 and channel 2 for the radio (RX and TX).

If the RX struct is located at address 0xF018, DMA1CFGH should be set to 0xF0 and DMA1CFGL should be set to 0x18. This struct takes up 8 bytes in memory. To make the structs consecutive, this means that the struct used for TX should start at address 0xF020.

There are no DMA2CFGH and DMA2CFGL. The DMA controller expects the struct to start at an address equal to DMA1CFGH:DMA1CFGL + 8. It is the programmer’s responsibility to make sure that the struct for channel 2 is placed 8 bytes after the struct for channel 1.

Example:

__xdata __no_init DMA_DESC dmaConfigRX @ 0xF018;  // Struct for the DMA channel 1 config.

__xdata __no_init DMA_DESC dmaConfigTX @ 0xF020;  // Struct for the DMA channel 2 config.

// Set DMA1CFGH = 0xF0 and DMA1CFGL = 0x18

SET_WORD(DMA1CFGH, DMA1CFGL, &dmaConfigRX);

The DMA controlle expect the struct for channel 2 to be at DMA1CFGH:DMA1CFGL + 8 = 0xF018 + 8 = 0xF020. If dmaConfigTX was placed on another address (for this example) the code would not work.

The struct for DMA channel 3 must be placed at DMA1CFGH:DMA1CFGL + 16 and for channel 4, @ DMA1CFGH:DMA1CFGL + 24

0 Marcelo Peres over 11 years ago in reply to Siri

Prodigy 35 points

Hi Siri,

Now you made it clear to me. Thanks.

Just for the record, if anyone ever need it, the code would be like this:

in the source file (*.c)

/*==== GLOBAL VARS============================================================*/

DMA_DESC dmaConfig0; // Struct for the DMA channel 0 config.
DMA_DESC dmaConfig1234[4]; // Struct for the DMA channels 1,2,3 and 4 config.

/*==== CODE============================================================*/

SET_WORD(DMA0CFGH, DMA0CFGL, &dmaConfig0);
SET_WORD(DMA1CFGH, DMA1CFGL, &dmaConfig1234);

in the header file (*.h)

/*==== EXPORTS ===============================================================*/

extern DMA_DESC dmaConfig0; // Struct for the DMA channel 0 config.
extern DMA_DESC dmaConfig1234[]; // Struct for the DMA channel 1,2,3 and 4 config.

0 Siri over 11 years ago in reply to Marcelo Peres

TI__Guru* 85791 points

HI Marcelo

That looks correct. I hope you are able to get all DMA channels up and running.

Siri

Other wireless

Other wireless technologies forum

DMA channel 2 setup on CC1110