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CC2538 ADC sampling rate and decimation factor

Koby Fruchtnis
Prodigy 10 points
Other Parts Discussed in Thread: CC2538

Hello.

I'm reviewing the single-chip solution spec of the CC2538.

The ADC sampling rate is stated as

 (decimation_rate + 16)*0.25 uSec

which calculates to 132 usec/sample, for 12 bit resolution.

Is this number correct? It seems quite slow, compared to similar chips, running at the same 4MHz ADC clock rate.

Can it be that the basic ADC resolution, 7-bit, is the cause of this performance?

  • 0
    TI__Guru**** 317180 points
    The number is correct. The ADC is a sigma-delta needing n internal samples to make one sample available for the user. With a decimation of 512, the decimation filter needs 512 internal samples (clocked at 4 MHz (0.25 us)) to generate one user sample.