TrxEB CC1120 Per Test Customization

First, do you need 100 kHz RX BW ? It's fairly wide when using 4.8 kbps.

The easiest way to do this is to type in what you need in SmartRF Studio and do a register export. You need all registers that are included in the export. Delete the register definitions under one of the existing ones, 1.2 kbps as an example and paste the new settings here. This way you don't need to rename variable names a lot of places in the code.

I'm in the middle of that exercise now......

a)the 1.2K example uses 58 registers, should I use them all or whatever SmratRF spits out?
b) is the file I'm supposed to modify "cc1120_per_test_api.c"
c) what is the ideal deviation and RXBW for 4.8kbps? I meant 20Khz in my post above, not 100Khz

Thanks

1) Use the registers that SmartRF Studio exports

3) See the Na settings under processors.wiki.ti.com/.../Category:WMBUS, those are 4.8 kbps. RXBW is also dependent on the accuracy of the xtal, see processors.wiki.ti.com/.../Category:Sub-1GHz

TER,

Below is my register export for the CC1120_long_range_mode_LRM project for the TrxEB. These values were from the link you posted above for WMBUS for 4.8kbps. This export, in fact no export of registers using SmartRF work on my EVB. When I re-flash if with the original project obj files the board works.

Do you see anything blatantly wrong with this register set?

static const registerSetting_t preferredSettings868[]=
{
{CC112X_IOCFG2, 0x06},
{CC112X_SYNC3, 0xaa},
{CC112X_SYNC2, 0xaa},
{CC112X_SYNC1, 0xf6},
{CC112X_SYNC0, 0x8d},
{CC112X_SYNC_CFG1, 0x09},
{CC112X_SYNC_CFG0, 0x0b},
{CC112X_DEVIATION_M, 0x3a},
{CC112X_MODCFG_DEV_E, 0x0a},
{CC112X_DCFILT_CFG, 0x1C},
{CC112X_PREAMBLE_CFG1, 0x14},
{CC112X_PREAMBLE_CFG0, 0x2A},
{CC112X_FREQ_IF_CFG, 0x40},
{CC112X_IQIC, 0xC6},
{CC112X_CHAN_BW, 0x11},
{CC112X_MDMCFG1, 0x46},
{CC112X_MDMCFG0, 0x05},
{CC112X_SYMBOL_RATE2, 0x63},
{CC112X_SYMBOL_RATE1, 0xA9},
{CC112X_SYMBOL_RATE0, 0x2A},
{CC112X_AGC_REF, 0x20},
{CC112X_AGC_CS_THR, 0x19},
{CC112X_AGC_GAIN_ADJUST, 0x00},
{CC112X_AGC_CFG3, 0x91},
{CC112X_AGC_CFG2, 0x20},
{CC112X_AGC_CFG1, 0xA9},
{CC112X_AGC_CFG0, 0xCF},
{CC112X_FS_CFG, 0x1a},
{CC112X_PA_CFG2, 0x7F},
{CC112X_PA_CFG1, 0x56},
{CC112X_PA_CFG0, 0x7C},
{CC112X_IF_MIX_CFG, 0x00},
{CC112X_FREQOFF_CFG, 0x22},
{CC112X_TOC_CFG, 0x0B},
{CC112X_FS_DIG1, 0x00},
{CC112X_FS_DIG0, 0x5F},
{CC112X_FS_CAL1, 0x40},
{CC112X_FS_CAL0, 0x0E},
{CC112X_FS_DIVTWO, 0x03},
{CC112X_FS_DSM0, 0x33},
{CC112X_FS_DVC0, 0x17},
{CC112X_FS_PFD, 0x50},
{CC112X_FS_PRE, 0x6E},
{CC112X_FS_REG_DIV_CML, 0x14},
{CC112X_FS_SPARE, 0xAC},
{CC112X_FS_VCO0, 0xB4},
{CC112X_XOSC5, 0x0E},
{CC112X_XOSC1, 0x03},
};

I forgot to mention that the 4.8 kbps settings are for 169 MHz so you have to adjust the FS_CFG register. 

But if I understand you correctly, the PER test doesn't work if you change the settings in the original file? Just as a sanity check, switch a couple of the settings already in the file. 

TER,

The long procedure below describes my efforts in detail..... I CANNOT go from SmartRF to an EVB application (CC1120_long_range_mode) successfully. There must be something else going on, a register that needs to be changed due to program mechanics, packet handling, etc... But I am having no success in simply changing RF parameters.

I need a test as follow; 915Mhz, 4.8kbps, 20-25kHz RXBW, +10dBm, but can't even get the canned examples to work.

1) Invoke SmartRF Studio7, no EVB connected.
2) Select CC1120 in off-line mode.
3) Press the “Register Reset” button, lower right 2X.
4) Select the 1st canned scenario under Generic 868/915/920MHz (1.2kbps,2-FSK, RXBW 25Khz (868)
a. Change carrier frequency to 915Mhz
b. Change Mod format to 2-GFSK
c. Change TX power to +10dBm
d. Leave everything else default
5) Select “Register Export”…..”trxEB RF Settings Performance Line” template.
6) Select “Copy to Clipboard”
7) Close SmartRF Studio
8) Register Setting are below;
a. // Packet length mode = Variable
b. // Whitening = false
c. // Address config = No address check
d. // Symbol rate = 1.2
e. // Packet bit length = 0
f. // Deviation = 3.997803
g. // Carrier frequency = 915.000000
h. // Manchester enable = false
i. // TX power = 10
j. // PA ramping = true
k. // RX filter BW = 25.000000
l. // Device address = 0
m. // Modulation format = 2-GFSK
n. // Packet length = 255
o. // Bit rate = 1.2
p. // Performance mode = High Performance
q. static const registerSetting_t preferredSettings[]=
r. {
s. {CC1120_IOCFG3, 0xB0},
t. {CC1120_IOCFG2, 0x06},
u. {CC1120_IOCFG1, 0xB0},
v. {CC1120_IOCFG0, 0x40},
w. {CC1120_SYNC_CFG1, 0x08},
x. {CC1120_MODCFG_DEV_E, 0x0B},
y. {CC1120_DCFILT_CFG, 0x1C},
z. {CC1120_PREAMBLE_CFG1, 0x18},
aa. {CC1120_IQIC, 0xC6},
bb. {CC1120_CHAN_BW, 0x08},
cc. {CC1120_MDMCFG0, 0x05},
dd. {CC1120_AGC_REF, 0x20},
ee. {CC1120_AGC_CS_THR, 0x19},
ff. {CC1120_AGC_CFG1, 0xA9},
gg. {CC1120_AGC_CFG0, 0xCF},
hh. {CC1120_FIFO_CFG, 0x00},
ii. {CC1120_FS_CFG, 0x12},
jj. {CC1120_PKT_CFG0, 0x20},
kk. {CC1120_PA_CFG2, 0x74},
ll. {CC1120_PKT_LEN, 0xFF},
mm. {CC1120_IF_MIX_CFG, 0x00},
nn. {CC1120_FREQOFF_CFG, 0x22},
oo. {CC1120_FREQ2, 0x72},
pp. {CC1120_FREQ1, 0x60},
qq. {CC1120_FS_DIG1, 0x00},
rr. {CC1120_FS_DIG0, 0x5F},
ss. {CC1120_FS_CAL1, 0x40},
tt. {CC1120_FS_CAL0, 0x0E},
uu. {CC1120_FS_DIVTWO, 0x03},
vv. {CC1120_FS_DSM0, 0x33},
ww. {CC1120_FS_DVC0, 0x17},
xx. {CC1120_FS_PFD, 0x50},
yy. {CC1120_FS_PRE, 0x6E},
zz. {CC1120_FS_REG_DIV_CML, 0x14},
aaa. {CC1120_FS_SPARE, 0xAC},
bbb. {CC1120_FS_VCO0, 0xB4},
ccc. {CC1120_XOSC5, 0x0E},
ddd. {CC1120_XOSC1, 0x03},
eee. };
9) Invoke IAR Workbench…open Project: "CC1120_long_range_mode"
10) Open file “CC1120_long_range_mode_reg_config.h”
11) Rename variables accordingly so as not to get any compile errors
12) Modify “CC1120_lrm_rx.c” and “CC1120_lrm_tx.c” so that RXBW register is not written to and FIXED (this would override my SmartRF settings, not allowing me to experiment). See line 408 of the “_rx.c” file!
13) Compile and program both of my EVBs.
14) All I get is missed packets on the RX side plot on the display.

Sorry, I assumed you used the PER test in www.ti.com/.../swrc219 based on your the title of your post. The long range mode example sets the RX BW to absolute minimum for the selected case and doing changes in this example requires more.

Why are you modifying this example and not the PER or easylink examples?

It appears that the Baseline version of IAR Workbench does not allow me to link the "Per_Test" (too large), so I choose the "long_range" project. I really didn't think it would make a difference. But I'll attempt what you are suggesting with the "Easylink".

Please keep in mind that I did take the RXBW into consideration AND I'm writing to additional registers based on what SmartRF indicates. It should have worked. See my step 12 above.

TER,

Again, default app works, exported registers do not. I think I've tried enough of your suggestions without success. Do you think someone can answer my question instead of just having me try things.

Please answer these questions;
1) does the register export look correct?
2) do I need to include more registers?
3) WHICH REGISTERS FOR THIS APPLICATION NEED TO BE INCLUDED BESIDES THOSE THAT ARE EXPORTED FROM SMARTRF STUDIO TO GET THIS TO WORK?

Thank you.

*****************NOTES FROM APPLICATION*******************

//! @file cc112x_easy_link_rx.c
//! @brief This program sets up an easy link between two trxEB's with
//! CC112x EM's connected.
//! The program can take any recomended register settings exported
//! from SmartRF Studio 7 without any modification with exeption
//! from the assumtions decribed below.
//
// Notes: The following asumptions must be fulfilled for
// the program to work:
//
// 1. GPIO2 has to be set up with GPIO2_CFG = 0x06
// PKT_SYNC_RXTX for correct interupt
// 2. Packet engine has to be set up with status bytes enabled
// PKT_CFG1.APPEND_STATUS = 1
//


***************ORIGINAL REGISTER SETTING**********************

static const registerSetting_t preferredSettings[] = {
{CC112X_IOCFG3, 0xB0},
{CC112X_IOCFG2, 0x06},
{CC112X_IOCFG1, 0xB0},
{CC112X_IOCFG0, 0xB0},
{CC112X_SYNC_CFG1, 0x0B},
{CC112X_DCFILT_CFG, 0x1C},
{CC112X_IQIC, 0xC6},
{CC112X_CHAN_BW, 0x08},
{CC112X_MDMCFG0, 0x05},
{CC112X_AGC_REF, 0x20},
{CC112X_AGC_CS_THR, 0x19},
{CC112X_AGC_CFG1, 0xA9},
{CC112X_AGC_CFG0, 0xCF},
{CC112X_FIFO_CFG, 0x00},
{CC112X_SETTLING_CFG, 0x03},
{CC112X_FS_CFG, 0x12},
{CC112X_PKT_CFG1, 0x05},
{CC112X_PKT_CFG0, 0x20},
{CC112X_PA_CFG2, 0x4F},
{CC112X_PA_CFG1, 0x56},
{CC112X_PA_CFG0, 0x1C},
{CC112X_PKT_LEN, 0xFF},
{CC112X_IF_MIX_CFG, 0x00},
{CC112X_FREQOFF_CFG, 0x22},
{CC112X_FREQ2, 0x6C},
{CC112X_FREQ1, 0x80},
{CC112X_FREQ0, 0x00},
{CC112X_FS_DIG1, 0x00},
{CC112X_FS_DIG0, 0x5F},
{CC112X_FS_CAL0, 0x0E},
{CC112X_FS_DIVTWO, 0x03},
{CC112X_FS_DSM0, 0x33},
{CC112X_FS_DVC0, 0x17},
{CC112X_FS_PFD, 0x50},
{CC112X_FS_PRE, 0x6E},
{CC112X_FS_REG_DIV_CML, 0x14},
{CC112X_FS_SPARE, 0xAC},
{CC112X_XOSC5, 0x0E},
{CC112X_XOSC3, 0xC7},
{CC112X_XOSC1, 0x07},
};


**************REGISTERS EXPORTED FROM SMARTRF***************
(note, those that are indented attempt to meet the two criteria from application notes)

static const registerSetting_t preferredSettings[]=
{
{CC112X_IOCFG3, 0xB0},
{CC112X_IOCFG2, 0x06},
{CC112X_IOCFG1, 0xB0},
{CC112X_IOCFG0, 0xB0},
{CC112X_PKT_CFG1, 0x05},
{CC112X_PKT_CFG0, 0x20},
{CC112X_SYNC_CFG1, 0x08},
{CC112X_DEVIATION_M, 0x48},
{CC112X_MODCFG_DEV_E, 0x0B},
{CC112X_CHAN_BW, 0x0A},
{CC112X_SYMBOL_RATE2, 0x63},
{CC112X_PA_CFG2, 0x74},
{CC112X_PA_CFG0, 0x7E},
{CC112X_FREQ2, 0x72},
{CC112X_FREQ1, 0x60},
};

TER,

The register set below worked for Easylink, but it did not work for Long Range Mode. I cannot figure out why.

// THIS WORKED IN THE EASYLINK APPLICATION  
// TX power = 10
// PA ramping = true
// Device address = 0
// Whitening = false
// Modulation format = 2-GFSK
// Address config = No address check
// Bit rate = 4.8
// Deviation = 5.004883
// Packet length mode = Variable
// RX filter BW = 20.000000
// Packet length = 255
// Performance mode = High Performance
// Packet bit length = 0
// Carrier frequency = 915.000000
// Symbol rate = 4.8
// Manchester enable = false

static const registerSetting_t preferredSettings868[]=
{
{CC112X_IOCFG3,            0xB0},
{CC112X_IOCFG2,            0x06},
{CC112X_IOCFG1,            0xB0},
{CC112X_IOCFG0,            0x40},
{CC112X_SYNC_CFG1,         0x08},
{CC112X_DEVIATION_M,       0x48},
{CC112X_MODCFG_DEV_E,      0x0B},
{CC112X_DCFILT_CFG,        0x1C},
{CC112X_IQIC,              0x00},
{CC112X_CHAN_BW,           0x08},
{CC112X_MDMCFG0,           0x05},
{CC112X_SYMBOL_RATE2,      0x63},
{CC112X_AGC_CS_THR,        0x19},
{CC112X_AGC_CFG1,          0xA9},
{CC112X_AGC_CFG0,          0xCF},
{CC112X_FIFO_CFG,          0x00},
{CC112X_FS_CFG,            0x12},
    {CC112X_PKT_CFG1,       0x05},  
{CC112X_PKT_CFG0,          0x20},
{CC112X_PA_CFG2,           0x74},
{CC112X_PA_CFG0,           0x7E},
{CC112X_PKT_LEN,           0xFF},
{CC112X_IF_MIX_CFG,        0x00},
{CC112X_FREQOFF_CFG,       0x22},
{CC112X_FREQ2,             0x72},
{CC112X_FREQ1,             0x60},
{CC112X_FS_DIG1,           0x00},
{CC112X_FS_DIG0,           0x5F},
{CC112X_FS_CAL1,           0x40},
{CC112X_FS_CAL0,           0x0E},
{CC112X_FS_DIVTWO,         0x03},
{CC112X_FS_DSM0,           0x33},
{CC112X_FS_DVC0,           0x17},
{CC112X_FS_PFD,            0x50},
{CC112X_FS_PRE,            0x6E},
{CC112X_FS_REG_DIV_CML,    0x14},
{CC112X_FS_SPARE,          0xAC},
{CC112X_FS_VCO0,           0xB4},
{CC112X_XOSC5,             0x0E},
{CC112X_XOSC1,             0x03},
};

The long range mode example is written to have maximum range using low datarate (600 bps) This example uses some tricks to achieve the range:

Frequency Compensation

Packet format: 3 byte PREAMBLE + 4 byte SYNC_1 + 1 byte payload (no CRC) + 1 byte PREAMBLE + 4 byte SYNC_2 + data payload
Receive mode is started with 12.5 kHz RX filter BW and FB2PLL enabled (i.e. wide enough to account for maximum frequency error caused by temperature drift and initial tolerance). After SYNC_1 is detected, register FREQOFF_EST gives the frequency offset between RX and TX units.
The RX unit is put in IDLE mode, the RX filter BW is reduced to 7.8 kHz, the error in FREQOFF_EST is written to register FREQOFF, SYNC_2 is written to the chip, and then RX is re-started. Note: FREQOFF and SYNC_2 cannot be updated in RX and must be doen with the chip in IDLE mode.
The TX unit transmits PREAMBLE, SYNC_1 and 1 byte payload (no CRC), goes to IDLE and re-starts TX with 1 byte PREAMBLE, SYNC_2 and data payload (Alternative is to write second preamble and SYNC_2 to TX FIFO and not re-start TX after SYNC_1 and 1 byte payload, but then CRC needs to be calculated in SW on the receiver side)

SYNC_1 = 0x2633D9CC
SYNC_2 = 0x930B51DE

From: processors.wiki.ti.com/.../Category:Sub-1GHz

As you see this code uses dual sync and an export from SmartRF Studio use only normal sync search.

I would recommend using the easylink example since this is the example that it's easiest to change settings etc.