Hi Team,
Going into production with an NFC device using the TI RF430CL330H, some variation with inductance on the board has been showing up. TI's reference board layout was used to design the board and there were no modifications to the loop antenna layout. Fine tuning the antenna's tuning capacitor has be figured out, however after the initial production runs there is some slop on the inductance.
Are there any recommendations for controlling the loop inductance during PCB fabrication?
How is the loop inductance controlled during the PCB fabrication for the RF430CL330H evaluation board?
Is it possible to get the original fab notes or PCB specs that have the instructions for the fab vendors for maintaining the loop inductance within some tolerance? It would be nice to see what those notes are so the same information can be used.
Thanks,
Dylan