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using RFIFG10 - Positive edge: Packet received with CRC OK.

Other Parts Discussed in Thread: CC1101

hi,



i am using a CC430 and i am trying to use the RFIFG10 interrupt to detect when i received a valid package. i have successfully used the CC430 RF example code which uses RFIFG9 and then manually checks the CRC. i was hoping that i could skip that by just using RFIFG10, but maybe i am interpreting the datasheet wrong:



the CC430 datasheet states:



RFIFG10 - Positive edge: Packet received with CRC OK.



i am enabling the ISR like such:





void receiveOn()



RF1AIES &= ~BITA;                          // positive edge of RFIFG10

RF1AIFG &= ~BITA;                         // Clear a pending interrupt

RF1AIE  |= BITA;                          // Enable the interrupt

Strobe( RF_SRX );                     

}




and my ISR looks like this:






#pragma vector=CC1101_VECTOR

__interrupt void CC1101_ISR(void)

{

switch(RF1AIV)

{

case RF1AIV_RFIFG10:

{

                 RxBufferLength = ReadSingleReg( RXBYTES );       

                 ReadBurstReg(RF_RXFIFORD, RxBuffer, RxBufferLength);

                 rssi = Mrfi_CalculateRssi(RxBuffer[RSSI_IDX]);          

                 __no_operation();

break;

}

}  

__bic_SR_register_on_exit(LPM3_bits);

}




the strange thing is that i get an interrupt only once. the packet received is valis as expectd, but i never get another ISR. when using the  RF1AIV_RFIFG9 example from the TI example code for the CC430, i get valid ISR's for every packet.



so what's the suggest ISR to use? RF1AIV_RFIFG10 or RF1AIV_RFIFG9 ? i would like to avoid getting an interrupt for packet that have no valid CSR or are not the correct device address. only for packets which are valid and actually for this device.



any help is greatly aprechiated.

thanks,

-r

  • Did you ever resolve this? I am running into the same problem, but can't figure out why.

    My post is here:

    http://e2e.ti.com/support/low_power_rf/f/155/p/114942/407745.aspx#407745

  • The issue has been confirmed in the factory. We have documented the behavior and will release the erratasheet update shortly. The erratum will be identified as RF1A8 in the erratasheet, and it has been described as follows:

    The intended behavior of RF1AIN10 is that it is set after the last byte is received [into RX FIFO] and reset after the first byte is read from the RX FIFO.
    However, the actual behavior is that the RF1AIN10 does not reset after the first byte of the RX FIFO is read.

    This is what causes the RFIFG10 interrupt to occur once and then never again. So to work around the problem they suggested...

    Use RF1AIN9 for RX handling instead. To verify the RX packet CRC, enable the RF1A option to append the CRC_OK bit to the end of the RX packet. The CRC_OK bit can be checked after reading out the RX FIFO buffer.

     

    Regards,

     

    Dung