Setting up TRF7960ATB with ISO14443B

Andreas -

this STM part is not a fully compliant ISO14443B type tag. it is compliant with the air interface and the framing of standard, but not more.

please find attached the .c and .h files you can use for reference, for this type of proprietary transponder.

these were done for the TRF7970A BoosterPack sitting on top of the MSP430G2553 LaunchPad - you should be able to leverage them to your advantage

SRIX4K.zip

Andreas - 

anti-collision is not required for ISO15693 or ISO14443B, but you should be able to recognize when a collision happens and deal with it. Single slot operations are straightforward as you say and if one happens, you can just indicate to the user to remove the extra tag and redo the REQB or WupB or Single Slot Inventory command

so the setup configuration for the TRF7960, -60A, -63A, for ISO14443B operations is: 

Register 0x00 ==> 0x21 (for +5VDC in and full power out) this is same thing you have in binary, in your post

Register 0x01 ==> 0x0C (for ISO14443B @ 106kbps data rate (also what you have indicated you have it set for and 106kbps is where you start; later, if the tag indicates support for 212kbps, 424kbps or 848kbps and you want to, you can bump it up)

you can also write Register 0x09 according to what you need for the rest of your system or let the IC do it for you.

for example, 0x00 in that register (10%, not using the SYS_CLK output for anything else) is generally OK for most ISO14443B tags, the range is 8% to 14%

Sending out REQB with FIFO reset at the start of the command sequence (the last three bytes are what goes out over the air)

EOTX IRQ handling with FIFO Reset (circled in red)

the SPI can be run slower than 2MHz, this is recommendation based on the subcarrier frequency of the response being 848kHz, which would put it (the SPI clock) above that and avoid issues with ISO14443A, generally, in the event the layout was poor and the data lines were routed close to the RX in lines.

the duty cycle of any data clock should strive for 50% duty cycle. i don't know that we characterized it much outside of that. the edges of the clock are important, so if you deviate, make sure everything shifts together (i would think this would be the first thing to think about)

the upper limit of the SPI is much higher than 2MHz. it really is dependent upon the load of lines themselves. when they are short (like on a PCB) the SPI can run faster, if they are long (we have some very creative designs around this topic over the years with long circuit boards and the sharing of the clock or the use of long cables), then it becomes an issue.

going lower than 2MHz, again, just to be clear - opens up the potential of corrupting the RX lines when using ASK tag responses....however, as ISO14443B is using BPSK, the likelyhood of this being an issue is lower, but on the other hand going too slow could result in the SPI timing being a bottleneck of sorts for data transfer.