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cc2530 - ADC - Decimation rate

Other Parts Discussed in Thread: CC2530

 

Hello,

 

I am going to use the ADC of the cc2530 and I don't understand at all its decimation rate parameter. What is it? And What is it used for? How is it related with the sampling rate?

 

Thanks in advace,

  • A simple approach to a ADC is the sigma delta as used in the Ti parts. The approach is to sample a single bit at a high rate (this is fixed)  thus spreading the noise over a wide bandwidth and then take some number of these samples to form (filter)  the output. The more samples used to form the output the lower the noise permiting more bits of resolution (there is no point to having more bits if the lower LSBs are in noise). You can choose 64, 128, 256, or 512 samples (descimation rate) to form the output, The more samples the higher the resolution but the conversion takes longer so the overal sample rate is lower. 

    Trivia: If you have a DSP or other high performance processor down stream you can sample at a higher rate with a low descimation rate (eg 7 bits DR=64) and then descimate the data further in the DSP to increase the effective number of bits. It is a trade of over the air packets, more bits but a lower rate versus 7 bits sent as a byte versus 12 bits sent as 2 bytes.