Other Parts Discussed in Thread: TEST2
Hi,
I have a design with one transmitter and two receiver . I have a strange problem that if the transmitter is operated while moving away from the receiver, at some distance both the receiver hangs and only the power cycling the receiver will make it work again. If i work within 3 or 4 mts range there won't be any problem and if the transmitter goes beyond certain range then the problem arises. Does it have anything to do with flushing out the Garbage data from FIFO ?
The testing environment is 40 x 50 feet open hall. The transmitter is hand held battery device operated with a 3.7V and receiver is connected with clean UPS power and no other electrical / RF interference.
The packet size I send is 3 bytes to both receivers.
Below are my RF settings.
The packet size I send is 3 bytes to both receivers.
/* Chipcon */
/* Product = CC2500 */
/* Chip version = E */
/* Crystal accuracy = 10 ppm */
/* X-tal frequency = 26 MHz */
/* RF output power = 0 dBm */
/* RX filterbandwidth = 541.666667 kHz */
/* Phase = 1 */
/* Datarate = 249.938965 kbps */
/* Modulation = (7) MSK */
/* Manchester enable = (0) Manchester disabled */
/* RF Frequency = 2432.999908 MHz */
/* Channel spacing = 199.951172 kHz */
/* Channel number = 0 */
/* Optimization = Sensitivity */
/* Sync mode = (3) 30/32 sync word bits detected */
/* Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX */
/* CRC operation = (1) CRC calculation in TX and CRC check in RX enabled */
/* Forward Error Correction = (0) FEC disabled */
/* Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word. */
/* Packetlength = 255 */
/* Preamble count = (2) 4 bytes */
/* Append status = 1 */
/* Address check = YES*/
/* FIFO autoflush = 0 */
/* Device address = 2 */
/* GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet */
/* GDO2 signal selection = (11) Serial Clock */
const unsigned char RF_rfSettings[42] =
{
// CC2500 registers data
0x07, // FIFOTHR
0x07, // MCSM2
0x30, // MCSM1
0x87, // WOREVT1
0x6B, // WOREVT0
0xF8, // WORCTRL
0x7F, // PTEST
0x3F, // AGCTEST
0x09, // FSCTRL1 Frequency synthesizer control.
0x00, // FSCTRL0 Frequency synthesizer control.
0x5D, // FREQ2 Frequency control word, high byte.
0x93, // FREQ1 Frequency control word, middle byte.
0xB1, // FREQ0 Frequency control word, low byte.
0x2D, // MDMCFG4 Modem configuration.
0x3B, // MDMCFG3 Modem configuration.
0x73, // MDMCFG2 Modem configuration.
0x22, // MDMCFG1 Modem configuration.
0xF8, // MDMCFG0 Modem configuration.
0x00, // CHANNR Channel number.
0x01, // DEVIATN Modem deviation setting (when FSK modulation is enabled).
0xB6, // FREND1 Front end RX configuration.
0x10, // FREND0 Front end RX configuration.
0x18, // MCSM0 Main Radio Control State Machine configuration.
0x1D, // FOCCFG Frequency Offset Compensation Configuration.
0x1C, // BSCFG Bit synchronization Configuration.
0xC7, // AGCCTRL2 AGC control.
0x00, // AGCCTRL1 AGC control.
0xB2, // AGCCTRL0 AGC control.
0xEA, // FSCAL3 Frequency synthesizer calibration.
0x0A, // FSCAL2 Frequency synthesizer calibration.
0x00, // FSCAL1 Frequency synthesizer calibration.
0x11, // FSCAL0 Frequency synthesizer calibration.
0x59, // FSTEST Frequency synthesizer calibration.
0x88, // TEST2 Various test settings.
0x31, // TEST1 Various test settings.
0x0B, // TEST0 Various test settings.
0x0B, // IOCFG2 GDO2 output pin configuration.
0x06, // IOCFG0D GDO0 output pin configuration. Refer to SmartRF® Studio User Manual for detailed pseudo register explanation.
0x05, // PKTCTRL1 Packet automation control.
0x05, // PKTCTRL0 Packet automation control.
0x70, // ADDR Device address.
0xFF // PKTLEN Packet length.
};
void RF_TxData (unsigned char fifo_length, unsigned char device_address)
{
unsigned char loop_e;
unsigned char tx_length, tx_address;
RF_WriteCommand (RF_SIDLE);
tx_length = fifo_length;
tx_address= device_address;
clr (PORTC, RF_CSN);
SPI0Buffer = RF_TXFIFO+0x40;
while (bit_is_set(PINB, RF_SO));
RF_WriteByte ();
SPI0Buffer = tx_length;
RF_WriteByte ();
SPI0Buffer = tx_address;
RF_WriteByte ();
tx_length--;
for (loop_e=0;loop_e<fifo_length;loop_e++)
{
SPI0Buffer = Tx_Data[loop_e];
RF_WriteByte ();
}
setb (PORTC, RF_CSN);
RF_ReadStatus (RF_TXBYTES);
RF_WriteCommand (RF_STX);
while (bit_is_clear(PINC, RF_GDO0));
while (bit_is_set(PINC, RF_GDO0));
RF_WriteCommand (RF_SIDLE);
RF_WriteCommand (RF_SFTX);
}
RECEIVER CODE :
void RF_RxData (void)
{
unsigned char loop_f;
RF_WriteCommand (RF_SRX); // receive mode
while (bit_is_clear(PINC, RF_GDO0)); // wait for data
if(bit_is_set(PINC, RF_GDO0)) // Check whether have data
{
while (bit_is_set(PINC, RF_GDO0)); // wait for receive complete
RF_ReadStatus (RF_RXBYTES);
if(s_data!=0)
{
clr (PORTC, RF_CSN);
SPI0Buffer = RF_RXFIFO+0xC0;
while(bit_is_set(PINB, RF_SO));
RF_WriteByte ();
RF_ReadByte ();
r_length = SPI0Buffer; // read first byte be fifo length
RF_ReadByte ();
r_address = SPI0Buffer; // read second byte be address
r_length--; // data length = fifo length -1
for(loop_f=0;loop_f<r_length;loop_f++)
{
RF_ReadByte ();
RF_Data[loop_f] = SPI0Buffer;
}
RF_ReadByte (); // Read RSSI data
RSSI = SPI0Buffer;
RF_ReadByte ();
CRC = SPI0Buffer;
setb (PORTC, RF_CSN);
if(CRC & 0x80)
{
if ((RF_Data[0] == 0xCC) && (RF_Data[2] == 0x55))
{
if (RF_Data[1] == 0x10)
{
TCCR1B = 0x00;
TMR_CNT = 0x00;
BED_UP ();
MOT_FLAG = 0x01;
}
else if (RF_Data[1] == 0x11)
{
TCCR1B = 0x00;
TMR_CNT = 0x00;
BED_DOWN ();
MOT_FLAG = 0x01;
}
else if ((RF_Data[1] == 0xFF) && (MOT_FLAG == 0x01))
{
BED_STOP ();
MOT_FLAG = 0x00;
}
}
}
}
}
RF_WriteCommand (RF_SIDLE);
RF_WriteCommand (RF_SFRX);
}