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Can't Read&Write single block when using TRF7960 about protocol ISO15693



Write 0x3F to interrupt ;ask register
Write 0x21 to CS Control
Write 0x02 to ISO Control
Write 0x13 to RX No response time
Write 0x21 to Modulator control register
Write 0x80 to TX Pulse Length
 Receiver Gain Adjust command

Then here's the bytes I send to read the tag's First Block data:

size = 11;
buf[0] = 0x8f; /* Flush FIFO */
buf[1] = 0x91; /* send with CRC */
buf[2] = 0x3d; /* write continous from 1D (TX len) */
buf[3] = (u8) (size >> 8); /* Length in FIFO */
buf[4] = (u8) (size << 4);
buf[5] = 0x22; /* ISO15693 flags */
buf[6] = 0x20; /* Read single block command */
buf[7] ~buf[14] //Tag ID
buf[15]=0x01; //Bluck Number

When I send this data, the IRQ status register's value is 0xA0; Then I delay more time when I receive the interrupt, I get the IRQ Status Register's value is 0xE0, than indicate the Chip is receiving and transporting data at the same time. I'm so confused about this problem.

  • Normal 0 false false false MicrosoftInternetExplorer4

    The IRQ Status 0xE0 don't show you, that the chip is receiving and transponding the same time, but that the chip has sent the command completely and has already began to receive the response.

    The delay seems to be long enough to give the system time to do both (transponding and start receiving).

    You should only wait until the next interrupt and then enter a interrupt service routine which takes action according the IRQ Status and resets the IRQ Status Register. You can also use a timer for timeout if now interrupt from the reader chip occurs in a adequate timespan. (Timeout if timer interrupt occures first.)

    If you do so in the IRQ Status Register will only show the bits, set after the last and before the current interrupt.

    Here some example:

        Msp430f2370CounterSet();                // TimerA set
        COUNT_VALUE = COUNT_1ms * 5;            // 5ms
        IRQ_CLR;                                // PORT2 interrupt flag clear
        IRQ_ON;
       
        Trf796xReset();                            // FIFO has to be reset before recieving the next response

        Trf796xRawWrite(&buf[0], 7);
       
        i_reg = 0x01;
        START_COUNTER;                            // start timer up mode for timeout
        irq_flag = 0x00;
        while(irq_flag == 0x00)                    // wait for end of TX interrupt or timeout
        {
        }
       
        rxtx_state = 30;                        // the response will be stored in buf[1] upwards
           
        Msp430f2370CounterSet();                // TimerA set
        COUNT_VALUE = COUNT_1ms * 10;   
        START_COUNTER;                            // start timer up mode for timeout
        i_reg = 0x01;
        while(i_reg == 0x01)                    // wait for end of RX interrupt or timeout
        {
        }

     

    In the interrupt service routine the values of irq_flag and i_register will be changed, so the while-loop will end after the interrupt. The reset of the IRQ Status register is also done in the ISR by reading out the register.

  • But I have another question, between the interrupt, how long should we wait? If we wait too long, I didn't know the data that in the register is still save. I attempt to read the FIFO before the Interrupt signal, only one byte is right, and the last byte is const value. And in my expriment, I cant't wait the Interrupt from the chip after send the CMD interrupt. What cause this problem? How long is the maximum time between two interrupt?

  • Normal 0 false false false MicrosoftInternetExplorer4

    Best would be to do the next step right after the interrupt. This can be done by a waiting-loop, which ends when a flag is changed in the ISR. Dependent on the length of data you want to send or receive there are at least 4 interrupts, which might be useful.

     

    TX active and only 3 bytes in FIFO (IRQ Status = 0xA0) => write further data to FIFO if you want to transceive more than 12 bytes (FIFO length)

    End of TX (IRQ Status = BIT7) => wait for RX

    RX active and 9 bytes already in FIFO (IRQ Status = 0x60) => read data from FIFO if more than 12 byte could be received

    End of RX (IRQ Status = Byte6) => read the last data from FIFO

     

    The exact timings you can find in the manual of the standard you use, but I would not use defined delays. Right at the end of TX/RX and right after the interrupt I would start the next necessary step.

  • See the question on the top, Use those CMD to read the data from the Card, but when I write the data(11 Bytes) in the FIFO register, the FIFO Status register returns 0x1d, that indecate I have write so many data in the register and I have write 13 bytes in the register, but I only write 11 bytes in the FIFO. How can I resolve this problem?

  • Normal 0 false false false MicrosoftInternetExplorer4

    Do you read the FIFO before replies?

    This could be problematic.

     

    Note: The FIFO should be read only after a tag reply. It cannot be read immediately after writing to it.” (Firmware Description)

     

    What is the aim of the experiment?

  • Thanks very much!

    The problem is found. In my project, I used LED. When I get it away form my board, the system will do well, Once I take it in the board, the chip cann't work correctly. The problem I haven't solve it, once I resolve it, I will share at this topic.

    This is a project about my course design, using RFID to manage the library.