On page 54 of the CC1120 user guide, it states:
"The CC112X provides a clock (IOCFGx.GPIOx_CFG= SERIAL_CLK(8)) that is used to set up new data on the data input line or sample data on the data output line. Data timing recovery is done automatically. The data pin is updated on the falling edge of the clock pin at the programmed symbol rate."
I am using the CC1120 in synchronous serial RX mode. I am using a logic analyzer to look at the data coming out of the GPIO pins.
My question is: Does the logic analyzer need to sample the data at the rising edge or the falling edge of the clock?
