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CC1312R: SPI Frame Format Issue

Nick Masur
Prodigy 205 points
Part Number: CC1312R
Other Parts Discussed in Thread: SYSCONFIG

Hello.

I am working with an external flash memory chip that only supports SPI modes 0 and 3 (POL = 0, PHA = 0 OR POL = 1, PHA = 0).

When I configure the SPI driver to use modes 0 or 3 (SPI_POL0_PHA0 or SPI_POL1_PHA0), there is a pause between each 8-bit frame, where the CS line is briefly pulled high, ending any communications with the external chip. See image.

When I configure the SPI driver to modes 1 or 2 (SPI_POL1_PHA1 or SPI_POL0_PHA1). there is no frame pause, but the external chip doesn't support these modes. See image.

The exchange should look as follows from the flash chip datasheet. See image.

I found a suggestion to change .minDmaTransferSize in spiCC26X2DMAHWAttrs from default 10 to 1, but this didn't seem to have an impact.

Any help greatly appreciated!

  • 0
    TI__Expert 3886 points

    Hi Nick,

    I think that there might be two options in this case.

    The first one would be to use Software Chip Select, meaning that the application takes care of the chip select assertion and de-assertion.

    In this case, you would use Sysconfig to configure the SPI peripheral in the 3-pin mode and then also set up a GPIO that can be used as the CS signal. Then, every time you want to interface with the external flash, you manually toggle the CS pin.

    The second option would be to consider using the NVS driver to interface with your external flash. It might make things easier for you, since it probably includes a lot of what you need for your application.

    BR,
    AndresM

  • 0
    Prodigy 205 points

    AndresM, thanks for the suggestions. I will try one or both to get around this issue.

    I'm curious, is the first image that I shared expected behavior? It seems to me that this makes modes 0 and 3 useless for most applications.

  • 0 in reply to Nick Masur
    TI__Expert 3886 points

    Hi Nick.

    Yes. That is the expected behavior.

    The main issue with SPI peripheral implementations is that they vary a lot. Different peripherals require different chip select assertion and de-assertion behaviors. For this reason, the SPI driver has been designed to operate transparently to the chip select, so that the user can implement a behavior suitable for the application and peripheral.

    BR,
    AndresM